Table of Contents
Advertisement
3.6
Test Interface Signals
Symbol
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_
TRST#
TEST
CLKVIEW
3.7
Power Supply Connections
3.7.1
Digital Supplies
Symbol
VDDO
DVDD
3.7.2
Analog Supplies
Symbol
AVDDH
AVDDL
Datasheet
Type
I
JTAG Clock.
I
JTAG TDI.
O
JTAG TDO.
I
JTAG TMS.
JTAG Reset. This is an active low reset signal for JTAG. This signal should be
I
terminated using a pull-down resistor to ground. It must not be left unconnected.
I
Factory Test Pin.
Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance testing.
O
The clock is selected by register programming.
Type
P
3.3 V I/O Power Supply.
P
1.5 V Digital Core Power Supply.
Type
P
3.3 V Analog Power Supply.
P
2.5 V Analog Power Supply.
Networking Silicon — 82540EP
Name and Function
Name and Function
Name and Function
15
Advertisement
Table of Contents
