R4/Rsr (Ram Select Register); R5/Port; R6/Port 6 (Port 6 I/O Data Register); R7/Port 7 (Port 7 I/O Data Register) - IBM MiEM78P468L Product Specification

6.1.5

R4/RSR (RAM Select Register)

(Address: 04h)
Bit 7
RBS1
Bits 7 ~ 6 (RBS1 ~ RBS0): determine which bank is activated among the four banks.
See the data memory configuration in Fig. 6-2. Use the BANK instruction (e.g. BABK 1)
to change banks.
Bits 5 ~ 0 (RSR5 ~ RSR0): used to select up to 64 registers (Address: 00~3F) in
indirect addressing mode. If no indirect addressing is used, the RSR can be used as an
8-bit general purpose read/writer register.
6.1.6 R5/Port 5 (Port 5 I/O Data and Page of Register Select
(Address: 05h)
Bit 7
R57
Bits 7~4: 4-bits I/O registers of Port 5
User can use the IOC50 register to define each bit either as input or output.
Bits 3~1: Not used
Bit 0 (IOCPAGE): change IOC5 ~ IOCF to another page
IOCPAGE = "0" : Page 0 (select register of IOC 50 to IOC F0)
IOCPAGE = "1" : Page 1 (select register of IOC 61 to IOC E1)
6.1.7

R6/Port 6 (Port 6 I/O Data Register)

(Address: 06h)
Bit 7
R67
Bits 7~0: 8-bit I/O registers of Port 6
User can use the IOC60 register to define each bit either as input or output.
6.1.8

R7/Port 7 (Port 7 I/O Data Register)

(Address: 07h)
Bit 7
R77
Bits 7~0: 8-bit I/O registers of Port 7
User can use the IOC70 register to define each bit either as input or output.
Product Specification (V1.5) 02.15.2007
(This specification is subject to change without further notice)
Bit 6 Bit 5 Bit 4
RBS0 RSR5 RSR4
Bit 6 Bit 5 Bit 4
R56 R55 R54
Bit 6 Bit 5 Bit 4
R66 R65 R64
Bit 6 Bit 5 Bit 4
R76 R75 R74
EM78P468N/EM78P468L
8-Bit Microcontroller
Bit 3 Bit 2 Bit 1
RSR3 RSR2 RSR1
Bit 3 Bit 2 Bit 1
− − −
Bit 3 Bit 2 Bit 1
R63 R62 R61
Bit 3 Bit 2 Bit 1
R73 R72 R71
Bit 0
RSR0
Bit 0
IOCPAGE
Bit 0
R60
Bit 0
R70
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