Tcc And Wdt Prescaler - IBM MiEM78P468L Product Specification

6.3 TCC and WDT Prescaler

Two 8-bit counters are available as prescalers for the TCC (Time Clock Counter) and
WDT (Watchdog Timer). The TCCP2~TCCP0 bits of the IOC71 register are used to
determine the ratio of the TCC prescaler. Likewise, the WDTP2~WDTP0 bits of the
IOC81 register are used to determine the WDT prescaler. The TCC prescaler
(TCCP2~TCCP0) is cleared by the instructions each time they are written into TCC,
while the WDT prescaler is cleared by the "WDTC" and "SLEP" instructions. Fig.7
depicts the circuit diagram of TCC and WDT.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be selected by
internal instruction clock or external signal input (edge selectable from the TCC control
register). If the TCC signal source is from the internal instruction clock, the TCC will be
incremented by 1 at every instruction cycle (without prescaler). If the TCC signal
source is from an external clock input, the TCC will be incremented by 1 at every falling
edge or rising edge of the TCC pin.
The Watchdog Timer is a free running on sub-oscillator. The WDT will keep on running
even after the oscillator driver has been turned off. During Normal mode, Green mode,
or Idle mode operation, a WDT time-out (if enabled) will cause the device to reset. The
WDT can be enabled or disabled at any time during the Normal mode and Green mode
by software programming. Refer to WDTE bit of IOC81 register. The WDT time-out
period is equal to (prescaler × 256 / (Fs/2)).
Instruction Clock = Fosc /2
Fosc: CPU operate frequency
TCC
Pin
WDTE (IOC81)
Product Specification (V1.5) 02.15.2007
(This specification is subject to change without further notice)
TE (IOC71)
Fig. 6-4(a) Block Diagram of TCC
WDT 8 bit counter
8 to 1 MUX
WDT Time out
Fig. 6-4(b) Block Diagram of WDT
EM78P468N/EM78P468L
MUX Prescaler
PSRE TCCP2~0
(IOC71) (IOC71)
TS (IOC71)
Prescaler
WDTP2~0
(IOC81)
8-Bit Microcontroller
Data Bus
TCC (R1)
8 to 1 MUX
TCC overflow interrupt
Fs/2
(Fs:Sub oscillator)
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