Post Codes - Advantech AIMB-251 Series User Manual

40. POST Codes

Please take reference to Phoenix-Award website for the latest post codes.
http://www.phoenix.com/en/Customer+Services/BIOS/AwardBIOS/Award+Error+Codes.ht
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40.1 Normal POST Code
EISA POST codes are typically output to port address 300h. ISA POST codes are output to
Note:
port address 80h.
Code (hex) Name
C0 Turn Off Chipset and
CPU test
C1 Memory Presence
C2 Early Memory
Initialization
C3 Extend Memory DRAM
select
C4 Special Display
Handling
C5 Early Shadow
C6 Cache presence test
CF CMOS Check
B0 Spurious
B1 Unclaimed NMI
BF Program Chip Set
E1-EF Setup Pages
1 Force load Default to
chipset
2 Reserved
Description
OEM Specific-Cache control cache
Processor Status (1FLAGS) Verification. Tests the following
processor status flags: Carry, zero, sign, overflow, the BIOS sets
each flag, verifies They are set, then turns each flag off and
verifies it is off.
Read/Write/Verify all CPU registers except SS, SP, and BP with
data pattern FF and 00. RAM must be periodically refreshed to
keep the memory from decaying. This function ensures that the
memory refresh function is working properly.
First block memory detect OEM Specific-Test to size on-board
memory. Early chip set initialization Memory presence test OEM
chip set routines clear low 64K of memory Test first 64K memory.
OEM Specific- Board Initialization
OEM Specific- Turn on extended memory Initialization
Cyrix CPU initialization, Cache initialization
OEM Specific- Display/Video Switch handling so that switch
handling display switch errors never occurs
OEM specific- Early shadow enable for fast boot
External cache size detection
CMOS checkup
If interrupt occurs in protected mode.
If unmasked NMI occurs, display Press F1 to disable NMI, F2
reboot.
To program chipset from defaults values
E1- Page 1, E2 - Page 2, etc.
Chipset defaults program
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User's Manual