Chipset Overview; I/O Controller Hub: Ich9R (X7Spa-H & X7Spa-Hf); I/O Controller Hub: Ich9 (X7Spa-L) - Supermicro Super X7SPA-L User Manual

X7SPA-L/X7SPA-H/X7SPA-HF User's Manual
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Chipset Overview

I/O Controller Hub: ICH9R (X7SPA-H & X7SPA-HF)
The I/O Controller ICH9R provides the data buffering and interface arbitration re-
quired for the system to operate efficiently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9R. The ICH9R supports
up to six PCI-Express lanes, six Serial ATA (SATA) ports and twelve USB 2.0 ports.
In addition, the ICH9R offers the Intel Matrix Storage Technology which provides
various RAID options for data protection and rapid data access. It also supports the
next generation of client management through the use of PROActive technology in
conjunction with Intel's next generation Gigabit Ethernet controller.
Intel ICH9R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include:
• Advanced Power Management
• SMBus 2.0 (I
• SST/PECI Fan Speed Control
• SPI Flash
• Low Pin Count (LPC) Interface

I/O Controller Hub: ICH9 (X7SPA-L)

The ICH9 I/O Controller offers all features of the ICH9R controller, however it will
only support up to 4 Serial ATA, & no RAID feature.
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