Figure 4.5:Dram Timing Control Setup Screen - Advantech MIC-3369C User Manual

Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When
this area is reserved, it cannot be cached. The user information of periph-
erals that need to use this area of system memory usually discusses their
memory requirements. The settings are: Enabled and Disabled (Default).
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI spec-
ification version 2.1. The settings are: Enabled (Default) and Disabled.
Init Display First
User can choose display priority on either peripheral PCI slot or on board
VGA chip. There are 2 options: PCI slot (Default) and On board
Figure 4.5: DRAM timing control setup screen
DRAM Timing Configure
This field lets you select system memory timing data. Manual and BY
SPD are two options. Default is "BY SPD"
CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. The settings are: 1.5, 2 and
2.5.
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