System Reset, Led Control Circuit; System Reset; Led Control Circuit; E 2 Prom For Pnp - NEC MultiSync LCD1550ME Service Manual

6. System reset, LED control circuit (Circuit diagram MAIN PWB)

6.1 System reset

System reset is performed by detecting the rising and falling of the 5V source voltage at I301.

6.2 LED control circuit

Green / amber is lit with the control signal of the LED GREEN and LED AMBER signal pin 32, 33 from
I302 (Circuit diagram MAIN PWB).
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7. E PROM for PnP (Circuit diagram MAIN PWB)
Data transfer between I304 and host.
There are two forms of communications protocol. In both, display capabilities are retrieved by the system
software during the boot-up and configuration time.
For the PC platform, this software layer is defined in the VESA BIOS Extension / Display Data Channel,
DDC2, standard.
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8. E PROM (Circuit diagram MAIN PWB)
Data transfer between I304 (24LC32) and CPU (I302) is effected through the IIC bus SCL (pin 14) and SDA
(pin 13) of I302. The data to be transferred to each device are stored in I304.
I303 control data.
OSD related setting data.
Other control data for service menu.
9. CPU circuit (Circuit diagram MAIN PWB)
I302 (MTV312MV64) functions as the CPU.
The source voltage for the device is 5.0V and the system clock frequency is 20MHz.

9.1 Detection of POWER switch status

The CPU identifies the ON status of the two power supplies. The identification is made when the power
supply is turned off. For example, if the power supply is turned off with the POWER switch, the POWER
switch must be turned on when activating the power supply again. If the power supply is turned off by
pulling out the power cord, then this power supply can be turned on by connecting the power cord,
without pressing the POWER switch.

9.2 Display mode identification

9.2.1 Functions
(1) Display mode identification
The display mode of input signal is identified based on Table 1, and according to the frequency and
polarity (HPOL, VPOL) of horizontal or vertical sync signal, presence of the horizontal or vertical
sync signal, and the discrimination signal (HSYNC_DETECT, VSYNC_DETECT).
When the mode has been identified through the measurement of horizontal and vertical frequencies,
the total number of lines is determined with a formula of "Horizontal frequency / Vertical frequency =
Total number of lines. "Final identification can be made by examining the coincidence of the obtained
figure with the number of lines for the mode identified from the frequency.
When the detected frequency if the sync signal has changed, the total number of lines should be
counted even through it is rge identified frequency in the same mode. Then, it is necessary to
examine whether the preset value for the vertical display position of Item 4-3 has exceeded the total
number of lines. If exceeded, a maximum value should be set up, which does not exceed the vertical
display position of Item 4-3.
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