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1
(3) LVDS SERIAL DATA
A
(a) Base configuration 24bit
D.OUT 1
CLKX
Previous Cycle
X3
B
R7-1
X2
B3-1
X1
G2-1
X0
R1-1
C
0±3ns
D
E
F
1
2
T
13.889ns (72.0MHz)
CLK
Next Cycle
R6-1
N.U.
B7
B2-1
N.U.
FVAL
LVAL
(VD)
G1-1
B1
B0
R0-1
G0
R5
2
3
B6
G7
G6
R7
B5
B4
B3
(HD)
G5
G4
G3
G2
R4
R3
R2
R1
N.U.: Not used
E400234503
DWG.
No.
3
4
1.41V
R6
1.075V
B2
G1
R0
SHEET
10
17
4
DF022-4PE-S1
A
B
C
D
E
F
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