Dio Register Format Of Fpga Code; B.4.5 - Advantech TPC-1071H User Manual

B.4.5

DIO register format of FPGA code

Base Address 0 R/W
Base Address 0 +
00H ~ 1EH
Base Address 0 +
1FH
Base Address 1
Base Address 1 + 00H
Base Address 1 + 01H
Base Address 1 + 02H
Base Address 1 + 03H
Base Address 1 +
04H~06H
Base Address 1 + 07H
Base Address 1 +
08H~10H
Base Address 1 + 11H
Embedded Platform PCI Digital I/O
BIT7 BIT6 BIT5
R
D7 D6 D5
Embedded Platform PCI Digital I/O
R/W BIT7 BIT6 BIT5
R
DI7 DI6
W
R
DO7 DO6 DO5
W
DO7 DO6 DO5
R
W
R
W
R
W
R
W
61 TPC-1071H/1271H/1571H/1771H User Manu-
BIT4 BIT3 BIT2
Reserved
FPGA Code Revision
D4 D3 D2
BIT4 BIT3 BIT2
DI
DI5 DI4 DI3 DI2
DI
DO
DO4 DO3 DO2
DO
DO4 DO3 DO2
Interrupt Enable Status
Interrupt Enable Register
Interrupt Triggering Status
Interrupt Triggering Register
Reserved
Interrupt Flag Status
Interrupt Flag Clear Register
Reserved
Buzzer Status
SPKS1 SPKSP0
Buzzer Register
SPKSPSSPKSPS0 SPKEN
BIT1 BIT0
D1 D0
BIT1 BIT0
DI1 DI0
DO1 DO0
DO1 DO0
DI1EN DI0EN
DI1EN DI0EN
DI1RF DI0RF
DI1RF DI0RF
DI1IF DI0IF
DI1IFCL DI0IFCL
SPKEN