Pll Circuits - Icom IC-208H Service Manual

4-2-7 UHF DRIVE AMPLIFIER CIRCUIT
(MAIN UNIT)
The RF signals from the low-pass filter (VCO board) pass
through the high-pass filter (L69, C119) and attenuator
(R135, R136, R138), and are then amplified at the pre-drive
(Q31) and drive (Q34, D14) amplifiers to obtain power that
IC14 can operate. The amplified signal is then applied to the
RF power amplifier (IC4).
4-2-8 UHF POWER AMPLIFIER CIRCUIT
(MAIN UNIT)
IC14 is a power module which has amplification output
capabilities of about 50 W. The RF signal from the drive
amplifier (Q34) is applied to IC14 (pin 1).
The amplified signals from the power amplifier (IC14, pin 4)
pass through the low-pass filter (L23, C190) and SWR
detector (D28, D34), antenna switching circuit (D40) and
high-pass filter (L47, L50, C284, C288, C292). The filtered
signals are passed through the low-pass filter (L51, L52,
L56, C295, C299) to suppress unwanted signals, and are
then applied to the antenna connector (CHASSIS unit J2).
Control voltage for the power amplifier (IC14, pin 2) are con-
trolled by the APC circuit to protect the power module from
a mismatched condition as well as to stabilise the output
power.
4-2-9 UHF APC CIRCUIT (MAIN UNIT)
The SWR detector circuit (D28, D34, L30) detects forward
signals and reflection signals at D28 and D34 respectively.
The combined voltage is at a minimum level when the
antenna impedance is matched at 50 Ω and is increased
when it is mismatched.
The detected voltage is applied to the APC amplifier (IC15,
pin 3) and compared with a reference voltage which is sup-
plied from the CPU (IC505) as a "PCON_U" D/A control sig-
nal.
• VHF PLL CIRCUIT
Loop
filter
X2
15.2 MHz
VHF VCO
Q3, D1, D2
16
Phase
15
detector
Programmable
Q2
divider
1
Buffer
Buffer
Q7
When antenna impedance is mismatched, the detected volt-
age exceeds the reference voltage. The output voltage of
the APC amplifier (IC15, pin 1) controls the bias voltage of
the power module (IC14) to reduce the output power via the
APC controller (IC15, D531).

4-3 PLL CIRCUITS

4-3-1 GENERAL (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and the receive local frequency. The PLL circuit
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by a crystal oscillator and the divided ratio of the program-
mable divider. IC1 and IC2 are dual PLL ICs that control both
VCO circuits for VHF and UHF.
4-3-2 VHF LOOP (VCO BOARD AND MAIN UNIT)
The generated signal at the V-VCO (Q3, D1, D2) enters the
PLL IC (MAIN unit; IC1, pin 8) via buffer-amplifiers (Q6, Q8)
and VCO switching circuit (D50) and is divided at the pro-
grammable divider section and is then applied to the phase
detector section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 15 (MAIN unit).
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (MAIN unit; IC5, Q9, Q10, D4), and
then applied to the V-VCO to stabilise the oscillated fre-
quency.
Q5
Buffer
Q4
Buffer
VCO
switch
D51
IC1 MB15A02PFV1
Programmable
Prescaler
counter
Shift register
45.6 MHz 2nd LO signal
to the FM IF IC (IC8, pin 3)
4 - 6
VCO
switch
D5
to the transmitter circuit
D6
to the 1st mixer circuit
Buffer
Q50
8
9
PLLCK
10
PLLDATA
11
PLLSTB1