Clock Generator - Clevo M720T Service Manual

Clock Generator

CLOCK GENERATOR
3 . 3 V S
L 3 9
H C B 1 60 8 K F -1 21 T 2 5
40m ils
L ayou t not e:
C 5 3 4 C 51 1 C 49 1
P LACE CRYS TAL WITH IN
5 00 M ILS O F
1 0 U _ 10 V _ 0 8 1 U _ 6 . 3 V _0 4 0 . 1 U _ 1 0V _ X 7 R _ 0 4
I CS9L PR363 EGLF
3 . 3 V M_ C L K
X 3
1 2
C 5 35 C 5 00
1 4 . 3 18 M H z
1 0 U _ 1 0V _0 8 1 U _6 . 3 V _ 04
C 4 72 C 4 71
27 P _ 5 0V _ 0 4 27 P _ 5 0V _ 0 4
R 2 8 4
[ 2 , 4 ] C LK _ B S E L 0
C L K _ I C H 48 R 2 7 9
[ 1 5 ] C LK _ I C H 4 8
C L K _ I C H 14 R 2 7 2
[ 1 5 ] C LK _ I C H 1 4
R 2 6 9
[ 2 , 4 ] C LK _ B S E L 2
[ 15 ] P M_ S T P C P U #
[ 1 5 ] P M _S T P P C I #
R 2 5 3
P C L K _ T P M R 2 6 6
[ 1 9] P C L K _ TP M
P C L K _ K B C R 2 6 7
[ 2 6] P C L K _ K B C
R 2 6 8
3 . 3 V S
P C L K _ I C H 33 R 2 7 1
[ 1 4 ] P C LK _ I C H 3 3
R 2 6 5
[ 1 0 , 1 1, 1 5 ] I C H _ S MB C L K 0
[ 1 0 , 1 1, 1 5 ] I C H _ S MB D A T 0
[ 1 5] C L K _ P W R G D
R 2 8 2
3 . 3 V S
FS LC FS LB F SL A C K5 05
H os t Clo ck
BS EL2
BS EL1 B SE L0
Fr eq uen cy
SAT A_CL KREQ#
0 0 0 26 6 MHz 106 6 MHz
(PEREQ1 #)
0 1 0 20 0 MHz 800 M Hz
0 1 1 16 6 MHz 667 M Hz
WL AN_C LKREQ #
(PEREQ3 #)
Layou t no te:
Insat lled : Di ffer enti al c lock
3 . 3 V M_ C L K
level is high er
R 29 6
1 K _ 1% _ 0 4
R 2 95 3 0 0_ 1 % _0 4
C 5 02 C 5 32
0 . 1 U _ 1 0V _X 7 R _ 0 4 0 . 1 U _ 10 V _ X 7R _0 4 C 4 82
0. 1 U _1 0 V _X 7 R _ 0 4
20m ils
U 2 2
C 4 8 0
11 49 Z 17 1 0 1
V D D 4 8 C P U T _ L 1F
0 . 1 U _ 10 V _ X 7R _0 4 45 48 Z 17 1 1 2
V D D A C P U C _ L 1F
52 Z 17 1 2 1
C P U T_ L 0
58 51 Z 17 1 3 2
X 1 C P U C _ L 0
X TA L _ I N
X TA L _ OU T
57 44 Z 17 1 4 3
X 2 P C I e T _L 8 / C P U I TP T_ L 2
43 Z 17 1 5 4
P C I e C _ L8 / C P U I T P C _ L 2
41 Z 17 3 8 R 30 6
P C I e T _L 7 / P E R E Q1 #
2. 2 K _ 0 4 40 Z 17 4 0 R 30 7
P C I eC _L 7 / P E R E Q2 #
33 _ 0 4 F S L A 12 39 Z 17 1 8 1
F S L A / U S B _4 8 MH z P C I e T_ L 6
38 Z 17 1 9 2
P C I e C _ L 6
33 _ 0 4 R E F _ 1 4 . 31 8 M 60
R E F 0_ 1 4 . 31 8 M
36 Z 17 4 1 1
P C I e T_ L 5
10 K _ 0 4 F S L C 61 35 Z 17 4 2 2
R E F 1/ F S LC / TE S T_ S E L P C I e C _ L 5
62 30 Z 17 2 2 2
C P U _ S T OP # P C I e T_ L 4
63 31 Z 17 2 3 1
P C I / P C I E X _ S T OP # P C I e C _ L 4
*1 0 K _0 4 S E L P C I E X 0 _ LC D # 5 26 Z 17 2 4 4
P C I C L K 3 / *S E L P C I E X 0 _ LC D # S A T A C L K T _ L
27 Z 17 2 5 3
S A TA C L K C _ L
Z 1 70 3
*3 3 _0 4 4 24 Z 17 2 6 4
P C I C L K 2 P C I e T_ L 3
25 Z 17 2 7 3
P C I e C _ L 3
33
*P E R E Q4 #
33 _ 0 4 Z 1 70 4 3
P C I C L K 1
22 Z 17 2 8 4
P C I e T_ L 2
23 Z 17 2 9 3
P C I e C _ L 2
10 K _ 0 4 R E Q _ S E L 64 32
* *P C I C L K 0/ R E Q_ S E L *P E R E Q3 #
19 Z 17 3 0 4
P C I e T_ L 1
S E L L C D _ 2 7 #
33 _ 0 4 9 20 Z 17 3 1 3
* S E LL C D _ 27 # / P C I C L K _F 5 P C I e C _ L 1
34
* P W R S A V E #
I T P _E N
10 K _ 0 4 8
P C I C L K _ F 4/ I T P _ E N
17 Z 17 3 2 4
2 7F I X/ L C D _ S S C G T/ P C I e T_ L 0
54 18 Z 17 3 3 3
S C LK 2 7 S S / L C D _ S S C GC / P C I e C _ L 0
55 16 F S LB
S D A TA F S L B / T E S T_ M OD E
R 2 9 3
10
V T T _P W R _ GD / P D #
14 Z 17 3 5 4
P C I e T _ L9 / D O T T_ 9 6 MH z L
*1 0 0K _ 0 4 15 Z 17 3 6 3
P C I e C _ L 9/ D OT C _ 9 6 MH z L
I C S 9 L P R 3 63 E G LF
Red words m ust be controlled by BIOS
PCI ECLK 6 (NEW CARD) M CH_CL KREQ # PCIECL K 1 ( 3GP LL )
(PEREQ2 #)
SAT ACL K PCIECL K 8 ( ICH)
PCI ECLK 2 (M INI ) L AN_CL KREQ # PCIECL K 3 ( MI NI_ 3G )
(PEREQ4 #)
PCI ECLK 4 (J M3 85 ) PCIECL K 5 ( GL AN)
C L K _ MC H _ B C L K
C L K _ MC H _ B C L K #
C L K _ C P U _B C L K
C L K _ C P U _B C L K #
3 . 3V M _ C L K
30m ils
C L K _ P C I E _ I C H
C L K _ P C I E _ I C H #
C 4 6 7 C 46 8 C 47 8
C L K _ P C I E _ J M3 8 0
1U _ 6. 3 V _ 0 4 0 . 1 U _ 1 0V _ X 7 R _ 04 * 10 U _1 0 V _0 8 C L K _ P C I E _ J M3 8 0#
C L K _ P C I E _ M I N I
C L K _ P C I E _ M I N I #
C L K _ P C I E _ G LA N
C L K _ P C I E _ G LA N #
4 R N 2 4 C LK _ MC H _ B C LK
C L K _ MC H _ B C L K [ 4 ]
3 4 P 2 R X 3 3 _0 4 C LK _ MC H _ B C LK # C L K _ S A T A
C L K _ MC H _ B C L K # [ 4 ]
C L K _ S A T A #
4 R N 2 2 C LK _ C P U _ B C L K
C L K _ C P U _ B C LK [ 2 ]
3 4 P 2 R X 3 3 _0 4 C LK _ C P U _ B C L K # C L K _ P C I E _ M I N I _ 3G
C L K _ C P U _ B C LK # [ 2]
C L K _ P C I E _ M I N I _ 3G #
C L K _ P C I E _ N E W _C A R D
2 R N 2 6 C LK _ P C I E _I C H
C L K _ P C I E _ I C H [ 1 4 ]
1 4 P 2 R X 3 3 _0 4 C LK _ P C I E _I C H # C L K _ P C I E _ N E W _C A R D #
C L K _ P C I E _ I C H # [ 1 4]
4 75 _ 1 %_ 0 4 C L K _ P C I E _ 3 GP L L
S A TA _C LK R E Q# [ 15 ]
C L K _ P C I E _ 3 GP L L #
4 75 _ 1 %_ 0 4
MC H _ C L K R E Q # [ 5 ]
4 R N 3 0 C LK _ P C I E _N E W _ C A R D C L K _ D R E F S S
C L K _P C I E _ N E W _ C A R D [ 2 0]
3 4 P 2 R X 3 3 _0 4 C LK _ P C I E _N E W _ C A R D # C L K _ D R E F S S #
C L K _P C I E _ N E W _ C A R D # [ 20 ]
C L K _ D R E F
4 R N 3 1 C LK _ P C I E _G L A N
C L K _ P C I E _ GL A N [ 2 3]
3 4 P 2 R X 3 3 _0 4 C LK _ P C I E _G L A N # C L K _ D R E F #
C L K _ P C I E _ GL A N # [ 23 ]
3 R N 3 2 C LK _ P C I E _J M 38 0
C L K _ P C I E _ J M3 80 [ 22 ]
C L K _ I C H 48
4 4 P 2 R X 3 3 _0 4 C LK _ P C I E _J M 38 0 #
C L K _ P C I E _ J M3 80 # [ 2 2 ]
1 R N 2 9 C LK _ S A T A P C L K _ K B C
C L K _ S A TA [ 1 3]
2 4 P 2 R X 3 3 _0 4 C LK _ S A T A #
C L K _ S A TA # [ 13 ]
P C L K _ I C H 33
1 R N 2 8 C LK _ P C I E _M I N I _ 3 G
C L K _ P C I E _ MI N I _3 G [ 1 9 ]
2 4 P 2 R X 3 3 _0 4 C LK _ P C I E _M I N I _ 3 G# P C L K _ T P M
C L K _ P C I E _ MI N I _3 G # [ 1 9]
LA N _ C L K R E Q # [ 2 3]
C L K _ I C H 14
1 R N 2 7 C LK _ P C I E _M I N I
C L K _ P C I E _ MI N I [ 2 0 ]
2 4 P 2 R X 3 3 _0 4 C LK _ P C I E _M I N I #
La yout not e:
C L K _ P C I E _ MI N I # [ 2 0]
W LA N _ C L K R E Q # [ 1 9, 2 0 ]
Pl ace term inati on c lose
1 R N 2 5 C LK _ P C I E _3 G P LL
C L K _ P C I E _ 3 GP L L [ 5 ] to ICS 9LPR 363DG LF
2 4 P 2 R X 3 3 _0 4 C LK _ P C I E _3 G P LL #
C L K _ P C I E _ 3 GP L L # [ 5]
1 R N 2 3 C LK _ D R E F S S
C L K _ D R E F S S [ 5 ]
2 4 P 2 R X 3 3 _0 4 C LK _ D R E F S S #
C L K _ D R E F S S # [ 5 ]
*1 0 m i l _ sh o rt
C L K _ B S E L 1 [ 2 , 4 ]
1 R N 2 1 C LK _ D R E F
C L K _ D R E F [ 5 ]
2 4 P 2 R X 3 3 _0 4 C LK _ D R E F #
C L K _ D R E F # [ 5]
Pi n5 P in9 Pin 14/1 5
SEL PCIE X0_L CD#/ SELL CD_2 7#=0 P CIEX 9
PCI 3 = 0 (l ow) SELL CD_2 7#=1 D OT96
SEL PCIE X0_L CD#/ SELL CD_2 7#=0 P CIEX 9
PCI 3 = 1 (h igh) SELL CD_2 7#=1 D OT96
[ 5 , 8 . . 16 , 1 9. . 27 , 3 1] 3 . 3V S
Schematic Diagrams
C 49 2 *1 0P _ 5 0 V _0 4
C 49 7 *1 0P _ 5 0 V _0 4
C 48 4 *1 0P _ 5 0 V _0 4
C 48 8 *1 0P _ 5 0 V _0 4
C 50 1 *1 0P _ 5 0 V _0 4
C 50 7 *1 0P _ 5 0 V _0 4
C 54 1 *1 0P _ 5 0 V _0 4
C 54 2 *1 0P _ 5 0 V _0 4
C 50 5 *1 0P _ 5 0 V _0 4
C 50 9 *1 0P _ 5 0 V _0 4
C 54 4 *1 0P _ 5 0 V _0 4
C 54 3 *1 0P _ 5 0 V _0 4
C 52 8 *1 0P _ 5 0 V _0 4
C 53 3 *1 0P _ 5 0 V _0 4
Sheet 18 of 40
C 51 2 *1 0P _ 5 0 V _0 4
C 51 9 *1 0P _ 5 0 V _0 4
Clock Generator
C 53 7 *1 0P _ 5 0 V _0 4
C 53 6 *1 0P _ 5 0 V _0 4
C 49 8 *1 0P _ 5 0 V _0 4
C 49 9 *1 0P _ 5 0 V _0 4
C 49 0 *1 0P _ 5 0 V _0 4
C 49 4 *1 0P _ 5 0 V _0 4
C 48 1 *1 0P _ 5 0 V _0 4
C 48 7 *1 0P _ 5 0 V _0 4
C 47 4 *1 0P _ 5 0 V _0 4
C 45 0 *1 0P _ 5 0 V _0 4
C 46 6 *1 0P _ 5 0 V _0 4
C 44 9 *1 0P _ 5 0 V _0 4
C 47 5 *1 0P _ 5 0 V _0 4
Pin 17/1 8
27F IX/S S
LCD (96M Hz)
PCI EX0
PCI EX0 D efau lt
Clock Generator B - 19