Clock Generator - Clevo E4105 Service Manual

Clock Generator

CLOCK GENERATOR
CLK_VCC1
1
5
17
24
29
XOUT 27
XIN 28
PR117 33_04 REF_0/CPU_SEL 30
20 CLK_BUF_REF14
31
CLK_SDATA
32
CLK_SCLK
2
8
9
12
21
26
33
SMBus
Q38
MTN7002ZHS3
D S
CLK_SCLK
10,11,20 SMB_CLK
PR121 2.2K_04
3.3VS
PR120 2.2K_04
D S CLK_SDATA
10,11,20 SMB_DATA
Q36
MTN7002ZHS3
CPU_SEL_During CK_PEWGD Latch Pinl
3.3VS
REF_0/CPU_SEL
PR118 *4.7k_04
PR119 10k_04
CLK_VCC2
U29
15
VDD_DOT VDD_SRC_I/O
18
VDD_27 VDD_CPU_I/O
VDD_SRC
VDD_CPU
3
VDD_REF DOT_96 CLK_BUF_DOT96_P 20
4
CLK_BUF_DOT96_N 20
DOT_96#
6
27M
7
27M_SS
XTAL_OUT
XTAL_IN
10
CLK_SATA 20
SRC_1/SATA
11
CLK_SATA# 20
SRC_1#/SATA#
13
CLK_PCIE_ICH 20
SRC_2
14
CLK_PCIE_ICH# 20
REF_0/CPU_SEL SRC_2#
SDA 16
CPU_STOP# PR122 2.2K_04
3.3VS
SCL CPU_STOP#
20
VSS_DOT CPU_1 19
VSS_27 CPU_1#
23
VSS_SATA CPU_0 CLK_BUF_BCLK_P 20
22
VSS_SRC CPU_0# CLK_BUF_BCLK_N 20
VSS_CPU
25
CLK_PWRGD
VSS_REF CKPWRGD/PD#
GND
3.3VS
SLG8SP585
9LRS3197
R328
10K_04
Q37 R322
G
42 CLKEN#
MTN7002ZHS3 1M_04
X4 FSX8L_14.31818MHz
XIN 2 1 XOUT
3.3VS
C435 C436
33p_50V_NPO_04 33p_50V_NPO_04
PIN_30 CPU_0 CPU_1
0(default) 133MHz 133MHz
1(0.7V-1.5V) 100MHz 100MHz
CLKGEN POWER
CLK_VCC1
L33 *HCB1608KF-121T25_32mil_short
C482 C475 C483
.1U_16V_04 1U_10V_06
.1U_16V_04
0.1uF near the every power pin
? ?
1.1VS_VTT
CLK_VCC2
L31
C491 C467 *HCB1608KF-121T25_32mil_short
.1U_16V_04
1U_10V_06
0.1uF near the every power pin
EMI
REF_0/CPU_SEL
C437 *10P_50V_04
EMI Capactior
3.3VS 10,11,12,13,19,20,21,22,23,24,25,26,28,29,30,31,32,34,35,36,41,42,45
1.1VS_VTT 4,6,7,19,20,21,24,25,26,38,40,41,42
Schematic Diagrams
3.3VS
VDD_I/O can be
Sheet 2 of 49
ranging from
1.05V to 3.3V
Clock Generator
Clock Generator B - 3