DFI NF4 SLI INFINITY User Manual page 96

3
BIOS Setup
Bottom of 32-bit [31:24] IO
This field is used to select the memory that will be remapped to an
address higher than 00E0.
1T/2T Memory Timing
2T timing which provides better system stability is supported in CG
or later revisions of the AMD Athlon
appear if you are using a CPU whose version is older than the CG
revision.
Auto Automatically detects the memory timing.
1T
2T
Read Preamble Value
When the DQS receiver is turned on, you can select the time prior
to the max-read DQS return. This will notify the controller on when
to enable its DQS receiver when awaiting the DRAM DQS driver
to turn on for a read. The controller will disable its DQS receiver
until the read preamble time and then enable its DQS receiver while
the DRAM asserts DQS.
Async Latency Value
This field is used to select a value equal to the maximum
asynchronous latency in the DRAM read round-trip loop.
Dynamic Idle Cycle Counter
This field is used to enable the dynamic idle cycle counter.
DRAM Bank Interleaving
The options are Enabled and Disabled.
Burst Length
Leave this in its default setting.
9 6
Sets the memory timing to Performance mode. Select this
mode for better system performance.
Sets the memory timing to Normal mode. Select this
mode if you encounter system instability.
TM
64 CPU. This field will not