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Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
9.4.5
Timer Compare Register (TCPR)
The Timer Compare Register (TCPR) is a 16-bit read/write register that contains the
value to be compared to the counter value. The counter value is compared against the
value in the TCPR on every timer clock after the Timer Enable (TE) bit is set. When the
compare matches, the TCF bit is set. If interrupts are enabled (the TCIE bit is set), an
interrupt is also generated. In Measurement modes, the TCPR is ignored.
9.4.6
Timer Control/Status Register (TCSR)
The Timer Control/Status Register (TCSR) is a 16-bit read/write register that controls
the timer and reflects its status. The control and status bits are described in the following
paragraphs (see Figure 9-3 on page 9-6).
9.4.6.1
Timer Enable (TE)—Bit 0
The Timer Enable (TE) bit is used to enable or disable the timer. Setting the TE bit (TE =
1) enables the timer and clears the Timer Count Register (TCR). The counter starts
counting according to the mode defined by TC[3:0]. Clearing the TE bit disables the
timer. The TE bit is cleared by hardware and software reset.
Note:
When all the three timers are disabled and not in GPIO mode, all three TIO
pins are tristated. In order to prevent undesired spikes on the TIO pins (when
switching from tri-state into active state), external pull-up or pull down
resistors should be tied to the TIO pins.
9.4.6.2
Timer Overflow Interrupt Enable (TOIE)—Bit 1
The Timer Overflow Interrupt Enable (TOIE) bit is used to enable the timer overflow
interrupts. The overflow interrupt is generated after the counter wraparound occurs;
that is, the counter value changes from $FFFF to $0000 when a new event occurs. Setting
the TOIE bit enables the overflow interrupts. When the TOIE bit is cleared, the overflow
interrupts are disabled. The TOIE bit is cleared by hardware and software reset.
9.4.6.3
Timer Compare Interrupt Enable (TCIE)–Bit 2
The Timer Compare Interrupt Enable (TCIE) bit is used to enable the timer compare
interrupts. The compare interrupt is generated after the counter matches the compare
register in the Timer, PWM, or Watchdog modes. If the TCPR is loaded with N, an
interrupt occurs after (N – M + 1) events, where M is TLR value. Setting the TCIE bit
enables the compare interrupts. When the TCIE bit is cleared, the compare interrupts are
disabled. The TCIE bit is cleared by hardware and software reset.
MOTOROLA
DSP56602 User's Manual
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Triple Timer Module
Triple Timer Module Programming Model
9-9
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