Advertisement
Triple Timer Module
Timer Modes of Operation
Note:
After the timer is enabled, the TIO pin output value is set equal to the INV bit
to guarantee the correct first pin transition.
9.5.4
Watchdog Modes
Two Watchdog modes are provided to ensure proper chip operation.
9.5.4.1
Mode 9—Watchdog, Output Pulse (Internal Clock)
The Watchdog Mode, Output Pulse Enable mode is selected when TC[3:0] is set to 1001.
In this mode, the counter is cleared after the TE bit is set and loaded with the TLR value
on the first timer pulse derived either from the DSP clock divided by two (CLK/2) or
from the prescaled clock input. The following timer pulses increment the counter. When
the counter matches the value of the TCPR, the TCF bit in TCSR is set, and if the TCIE bit
is set, a compare interrupt is generated and the count is continued. At the next timer
pulse, the counter is loaded with TLR value (if TRM is set) and the count is resumed. If
the TRM bit is cleared, the counter continues to be incremented on each timer pulse. This
process is repeated until the timer is disabled. The counter is reloaded whenever the TLR
is written with a new value while the timer is enabled. When counter wraparound
occurs, the TOF bit in the TCSR is set, and if the TOIE bit is set, an overflow interrupt is
generated. At the same time, a pulse is output on the TIO pin with the width equal to the
timer clock period. The pulse polarity is determined by the INV bit. The counter contents
can be read at any time by reading the TCR.
Note:
In this mode, the internal hardware preserves the TIO value and direction for
an additional 2.5 internal clock cycles after reset was activated. This ensures a
valid length reset when the TIO is used as input to the RESET pin.
9.5.4.2
Mode 10—Watchdog, Output Toggle (Internal Clock)
The Watchdog Mode, Output Toggle Enable mode is selected when TC[3:0] is set to
1010. In this mode, the counter is cleared after the TE bit is set and loaded with the TLR
value on the first timer pulse derived either from the DSP clock divided by two (CLK/2)
or from the prescaled clock input. The following timer pulses increment the counter.
When the counter matches the value of the TCPR, the TCF bit in TCSR is set, and if the
TCIE bit is set, a compare interrupt is generated and the count is continued. At the next
timer pulse, the counter is loaded with the TLR value (if the TRM bit is set) and the count
is resumed. If the TRM bit is cleared, the counter continues to be incremented on each
timer pulse. This process is repeated until the timer is disabled. The counter is reloaded
whenever the TLR is written with a new value while the timer is enabled. When counter
wraparound occurs, the TIO output pin is toggled, the TOF bit in the TCSR is set, and if
the TOIE is set, an overflow interrupt is generated. The TIO polarity is determined by the
INV bit. On the first transaction, the TIO output is set if the INV bit is cleared, or cleared
if the INV bit is set. The counter contents can be read at any time by reading the TCR.
9-18
Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
DSP56602 User's Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Advertisement
