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Triple Timer Module
Triple Timer Module Programming Model
9.4.6.9
Data Output (DO)—Bit 12
The Data Output (DO) bit writes data to the TIO pin. When the GPIO mode is enabled
(TC0–TC3 are all cleared) and DIR = 1, the TIO pin acts as data output. Writing the DO
bit writes the data to the TIO pin. If the INV bit is set, the data on the TIO pin is inverted.
When GPIO mode is disabled, writing the DO bit has no effect. The DO bit is cleared by
hardware and software reset.
9.4.6.10
Timer Overflow Flag (TOF)—Bit 13
The Timer Overflow Flag (TOF) bit, when set, indicates that counter wraparound has
occurred. The Timer Overflow Flag bit is cleared when writing a one into the TOF bit.
Writing a 0 into the TOF bit has no effect. The bit is also cleared when the timer overflow
interrupt is serviced (timer overflow interrupt acknowledge). The TOF bit is cleared by
hardware and software reset, by the STOP instruction, and by timer disabling (TE = 0).
9.4.6.11
Timer Compare Flag (TCF)—Bit 14
In the Timer, PWM, and Watchdog modes, the Timer Compare Flag (TCF) bit when set
indicates that (N – M + 1) events are counted, where N is the value in the compare
register and M is TLR value. In the Measurement modes, the TCF bit when set indicates
that the measurement has been completed. The Timer Compare Flag bit is cleared when
writing a 1 into the TCF bit. Writing a 0 into the TCF bit has no effect. The bit is cleared
also when the Timer Compare interrupt is serviced (timer compare interrupt
acknowledge). The TCF bit is cleared by hardware and software reset, the STOP
instruction, and also by timer disabling (TE = 0).
Notes:
1. Writing a 0 in the TOF or TCF bit can be done with the Bit Test and Clear
(BCLR) instruction. The state of the tested bit is stored in the Carry bit of
the Status Register (SR).
2. TOF and TCF are cleared by writing logic 1 to the specific bit. In order to
assure that only the desired bit is cleared, the programmer should not use
the BSET command. The proper way to clear these bits is to write a logic 1
to the flag to be cleared and 0 to the other flag, using the MOVEP
instruction.
9.4.6.12
Prescaled Clock Enable (PCE)—Bit 15
The Prescaled Clock Enable (PCE) bit is used to select the prescaled clock as the timer
source clock. When PCE is cleared the timer uses either internal (CLK/2) or external
(TIO) source clock as determined by the timer operating mode. When PCE is set, the
prescaler output is used as the timer source clock for the counter regardless of the timer
operating mode.
The PCE bit is cleared by hardware and software reset.
9-12
Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
DSP56602 User's Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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