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Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
Notes:
1. To ensure proper functionality, the PCE bit should be changed only when
the timer is disabled.
2. The source clock for the prescaler is determined only by the Prescaler
Source bits (PS0–PS1) of the TPLR. Therefore, a timer can be clocked by
prescaled clock derived from the TIO of another timer.
9.4.6.13
Reserved Bit—Bit 3
Bit 3 of the TCSR is reserved. It is read as 0 and should be written with 0 for future
compatibility.
9.5
TIMER MODES OF OPERATION
The DSP56602 timers have the following four modes of operation:
• Timer
• Measurement
• Pulse Width Modulation
• Watchdog
Table 9-3 summarizes these modes, and the following paragraphs describe these modes
in detail.
Mode
0
Timer Mode, No Output (Internal Clock)
1
Timer Mode, Output Pulse Enable (Internal Clock)
2
Timer Mode, Output Toggle Enable (Internal Clock)
3
Timer Mode, Output Toggle Enable (External Clock)
4
Pulse Width Measurement Mode
5
Period Measurement Mode
6
Capture Mode
7
Pulse Width Modulation Mode, Output Toggle Enable
8
(Reserved)
MOTOROLA
Table 9-3 Timer Mode Summary
Mode Description
DSP56602 User's Manual
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Triple Timer Module
Timer Modes of Operation
Mode Type
TC[3:0]
Timer
0000
Timer
0001
Timer
0010
Timer
0011
Measurement
0100
Measurement
0101
Measurement
0110
PWM
0111
(Reserved)
1000
9-13
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