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Motorola DSP56602 User Manual page 14

Triple timer module

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Triple Timer Module
Timer Modes of Operation
Table 9-3 Timer Mode Summary (continued)
Mode
9
Watchdog Mode, Output Pulse Enable (Internal Clock)
10
Watchdog Mode, Output Toggle Enable (Internal Clock)
11
(Reserved)
12
(Reserved)
13
(Reserved)
14
(Reserved)
15
(Reserved)
9.5.1
Timer Modes
Timer modes allow using the timers to measure the duration of an event.
9.5.1.1
Mode 0—Timer, No Output (Internal Clock)
This mode is selected when TC[3:0] is set to 0000. In this mode, the counter is cleared
after the TE bit is set and loaded with the TLR value on the first timer pulse derived
either from the DSP clock divided by two (CLK/2) or from the prescaled clock input.
The following timer pulses increment the counter. When the counter matches the value
contained by the TCPR, the TCF bit in TCSR is set and, if the TCIE is set, a compare
interrupt is generated. At the next timer pulse, the counter is loaded with TLR value (if
TRM is set) and the count is resumed. If TRM is cleared, the counter continues to be
incremented on each timer pulse. If counter wraparound occurs, the TOF bit is set, and if
the TOIE is set, an overflow interrupt is generated. This process is repeated until the
timer is disabled (the TE bit is cleared). The counter contents can be read at any time by
reading the TCR.
9.5.1.2
Mode 1—Timer, Output Pulse (Internal Clock)
This mode is selected when TC[3:0] is set to 0001. In this mode, the counter is cleared
after the TE bit is set and loaded with the TLR value on the first timer pulse derived
either from the DSP clock divided by two (CLK/2) or from the prescaled clock input.
The following timer pulses increment the counter. When the counter matches the value
contained by the TCPR, the TCF bit in TCSR is set, and if the TCIE is set, a compare
interrupt is generated. At the next timer pulse, the counter is loaded with TLR value (if
TRM is set) and the count is resumed. If TRM is cleared, the counter continues to be
incremented on each timer pulse. This process is repeated until the timer is disabled
9-14
Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
Mode Description
DSP56602 User's Manual
For More Information On This Product,
Go to: www.freescale.com
Mode Type
TC[3:0]
Watchdog
1001
Watchdog
1010
(Reserved)
1011
(Reserved)
1100
(Reserved)
1101
(Reserved)
1110
(Reserved)
1111
MOTOROLA

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