Texas Instruments PCI7621 Data Manual
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Texas Instruments PCI7621 Data Manual

Texas Instruments PCI7621 Data Manual

Dual/single socket cardbus and ultramedia controller with integrated 1394a-2000 ohci two-port phy/link-layer controller with dedicated flash media socket
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PCI7621/PCI7611/PCI7421/PCI7411
Dual/Single Socket CardBus and UltraMedia Controller
With Integrated 1394a 2000 OHCI Two Port
PHY/Link Layer Controller With Dedicated Flash Media
Socket
Data Manual
June 2004
Connectivity Solutions
SCPS081

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  • Page 1 PCI7621/PCI7611/PCI7421/PCI7411 Dual/Single Socket CardBus and UltraMedia Controller With Integrated 1394a 2000 OHCI Two Port PHY/Link Layer Controller With Dedicated Flash Media Socket Data Manual June 2004 Connectivity Solutions SCPS081...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

  • Page 3: Table Of Contents

    ......1−1 1.1.1 PCI7621 Controller ....... . . 1−1 1.1.2...
  • Page 4 Section Title Page 3.5.8 SPKROUT and CAUDPWM Usage ....3−9 3.5.9 LED Socket Activity Indicators ......3−9 3.5.10 CardBus Socket Registers...
  • Page 5 Section Title Page PC Card Controller Programming Model ......4−1 PCI Configuration Register Map (Functions 0 and 1) .
  • Page 6 Section Title Page 4.42 Next Item Pointer Register ........4−31 4.43 Power Management Capabilities Register...
  • Page 7 Section Title Page OHCI Controller Programming Model ....... 7−1 Vendor ID Register .
  • Page 8 Section Title Page 8.15 Vendor ID Register ......... . 8−12 8.16 Host Controller Control Register...

  • Page 9: Section Title Page

    Section Title Page 10.4 Vendor-Dependent Register ........10−6 10.5 Power-Class Programming...
  • Page 10 Section Title Page 12.16 Slot Information Register ........12−10 12.17 Capability ID and Next Item Pointer Registers .
  • Page 11 Section Title Page 14 Electrical Characteristics ......... . 14−1 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges...
  • Page 12 List of Illustrations Figure Title Page 2−1 PCI7621 GHK/ZHK-Package Terminal Diagram ..... 2−1 2−2 PCI7421 GHK/ZHK-Package Terminal Diagram .....
  • Page 13 List of Tables Table Title Page 1−1 Terms and Definitions ......... . . 1−7 2−1 Signal Names by GHK Terminal Number...

  • Page 14: Table Title Page

    Table Title Page 3−18 Function 4 Power-Management Registers ......3−26 3−19 Function 5 Power-Management Registers .

  • Page 15: Cardbus Socket Registers

    Table Title Page 5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description ........... . 5−20 5−14 ExCA Card Detect and General Control Register Description .
  • Page 16 Table Title Page 8−11 Host Controller Control Register Description ......8−13 8−12 Self-ID Count Register Description ....... . 8−15 8−13 Isochronous Receive Channel Mask High Register Description .
  • Page 17 Table Title Page 11−5 Latency Timer and Class Cache Line Size Register Description ..11−5 11−6 Header Type and BIST Register Description ......11−6 11−7 Flash Media Base Address Register Description...
  • Page 18 Table Title Page 13−15 Smart Card Configuration 1 Register Description ....13−16 13−16 Smart Card Configuration 2 Register Description ....13−17 xviii...

  • Page 19: Introduction

    Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard (Release 8.1). The PCI7621 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports any combination of Smart Card, Flash Media, 16-bit, CardBus, and USB custom card interface PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

  • Page 20: Pci7421 Controller

    Function 5 of the PCI7621 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards.

  • Page 21: Pci7411 Controller

    1.1.7 Power Switch Interface The PCI7x21/PCI7x11 controller also has a three-pin serial interface compatible with the Texas Instruments TPS2228 (default), TPS2226, TPS2224, and TPS2223A power switches. All four power switches provide power to the CardBus socket(s) on the PCI7x21/PCI7x11 controller. The power to each dedicated socket is controlled through separate power control pins.

  • Page 22: Features

    1.2 Features The PCI7x21/PCI7x11 controller supports the following features: • PC Card Standard 8.1 compliant • PCI Bus Power Management Interface Specification 1.1 compliant • Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant • PCI Local Bus Specification Revision 2.3 compliant •...

  • Page 23: Related Documents

    PCI14xx Implementation Guide for D3 Wake-Up • PCI to PCMCIA CardBus Bridge Register Description • Texas Instruments TPS2224 and TPS2226 product data sheet, SLVS317 • Texas Instruments TPS2223A product data sheet, SLVS428 • Texas Instruments TPS2228 product data sheet, SLVS419 •...

  • Page 24: Trademarks

    SmartMedia Standard 2000, May 19, 2000 1.4 Trademarks Intel is a trademark of Intel Corporation. TI and MicroStar BGA are trademarks of Texas Instruments. FireWire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Corporation of America.

  • Page 25: Terms And Definitions

    A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI7621 when the adapter and media are both inserted.
  • Page 26 1−8...

  • Page 27: Terminal Descriptions

    The PCI7x21/PCI7x11 controller is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a pin diagram of the PCI7621 package. Figure 2−2 is a pin diagram of the PCI7421 package. Figure 2−3 is a pin diagram of the PCI7611 package.

  • Page 28: Pci7421 Ghk/Zhk-Package Terminal Diagram

    AD27 VCCP C/BE3 IDSEL AD19 C/BE2 STOP C/BE1 VCCP C/BE0 TPB0N TPA0N TPB1N TPA1N VDPLL AD30 AD29 AD26 AD24 AD23 AD18 FRAME PERR AD15 AD11 TPB0P TPA0P TPB1P AVDD TPA1P (TEST3) AD31 AD28 AD25 AD22 AD17 IRDY SERR AD14 AD10 AGND TPBIAS0 AGND...

  • Page 29: Pci7611 Ghk/Zhk-Package Terminal Diagram

    AD27 VCCP C/BE3 IDSEL AD19 C/BE2 STOP C/BE1 VCCP C/BE0 TPB0N TPA0N TPB1N TPA1N VDPLL AD30 AD29 AD26 AD24 AD23 AD18 FRAME PERR AD15 AD11 TPB0P TPA0P TPB1P AVDD TPA1P (TEST3) AD31 AD28 AD25 AD22 AD17 IRDY SERR AD14 AD10 AGND TPBIAS0 AGND...

  • Page 30: Pci7411 Ghk/Zhk-Package Terminal Diagram

    Table 2−1 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for both CardBus and 16-bit PC Cards for the PCI7421 and PCI7621 GHK packages. Table 2−2 and Table 2−3 list the terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the GHK package;...

  • Page 31: Signal Names By Ghk Terminal Number

    Table 2−1. Signal Names by GHK Terminal Number SIGNAL NAME SIGNAL NAME TERMINAL TERMINAL TERMINAL TERMINAL NUMBER NUMBER NUMBER NUMBER CardBus PC Card 16-Bit PC Card CardBus PC Card 16-Bit PC Card A_CAUDIO A_BVD2(SPKR) A_CAD22 A_A4 A_CVS1 A_VS1 A_CAD19 A_A25 A_CAD25 A_A1 A_CFRAME...
  • Page 32 Table 2−1. Signal Names by GHK Terminal Number (Continued) SIGNAL NAME SIGNAL NAME TERMINAL TERMINAL TERMINAL TERMINAL NUMBER NUMBER CardBus PC Card 16-Bit PC Card CardBus PC Card 16-Bit PC Card A_CC/BE2 A_A12 V CC V CC A_CPERR A_A14 V CC V CC A_CAD6 A_D13...
  • Page 33 Table 2−1. Signal Names by GHK Terminal Number (Continued) SIGNAL NAME SIGNAL NAME TERMINAL TERMINAL TERMINAL TERMINAL NUMBER NUMBER CardBus PC Card 16-Bit PC Card CardBus PC Card 16-Bit PC Card SC_CLK SC_CLK B_CC/BE0 B_CE1 SC_VCC_5V SC_VCC_5V VR_PORT VR_PORT V CC V CC DATA DATA...
  • Page 34 Table 2−1. Signal Names by GHK Terminal Number (Continued) SIGNAL NAME SIGNAL NAME TERMINAL TERMINAL TERMINAL TERMINAL NUMBER NUMBER CardBus PC Card 16-Bit PC Card CardBus PC Card 16-Bit PC Card AD18 AD18 GRST GRST FRAME FRAME PERR PERR RI_OUT/PME RI_OUT/PME AD15 AD15...

  • Page 35: Cardbus Pc Card Signal Names Sorted Alphabetically

    Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically TERMINAL TERMINAL TERMINAL TERMINAL SIGNAL NAME SIGNAL NAME SIGNAL NAME SIGNAL NAME NUMBER NUMBER NUMBER NUMBER A_CAD5 A_CPERR B_CAD30 A_CAD6 A_CREQ B_CAD31 A_CAD7 A_CRST B_CAUDIO A_CAD8 A_CSERR B_CBLOCK A_CAD9 A_CSTOP B_CC/BE0 A_CAD10 A_CSTSCHG B_CC/BE1...
  • Page 36 Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically (Continued) TERMINAL TERMINAL TERMINAL SIGNAL TERMINAL SIGNAL NAME SIGNAL NAME SIGNAL NAME NUMBER NUMBER NUMBER NAME NUMBER SD_CMD TPBIAS0 SD_DAT0 TPBIAS1 PCLK SD_DAT0 TPB0N PC0(TEST1) SD_DAT1 TPB0P PC1(TEST2) SD_DAT1 TPB1N PC2(TEST3) SD_DAT2 TPB1P PERR...

  • Page 37: Bit Pc Card Signal Names Sorted Alphabetically

    Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically SIGNAL TERMINAL TERMINAL TERMINAL TERMINAL SIGNAL NAME SIGNAL NAME SIGNAL NAME NAME NUMBER NUMBER NUMBER NUMBER A_A5 A_INPACK B_CE1 A_A6 A_IORD B_CE2 A_A7 A_IOWR B_D0 A_A8 A_OE B_D1 A_A9 A_READY(IREQ) B_D2 A_A10 A_REG B_D3...
  • Page 38 Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued) TERMINAL TERMINAL TERMINAL SIGNAL TERMINAL SIGNAL NAME SIGNAL NAME SIGNAL NAME NUMBER NUMBER NUMBER NAME NUMBER SD_CMD TPBIAS0 SD_DAT0 TPBIAS1 PCLK SD_DAT0 TPB0N PC0(TEST1) SD_DAT1 TPB0P PC1(TEST2) SD_DAT1 TPB1N PC2(TEST3) SD_DAT2 TPB1P PERR...

  • Page 39: Detailed Terminal Descriptions

    2.1 Detailed Terminal Descriptions Please see Table 2−4 through Table 2−19 for more detailed terminal descriptions. The following list defines the column headings and the abbreviations used in the detailed terminal description tables. • I/O Type: − I = Digital input −...

  • Page 40: Power Supply Terminals

    Table 2−4. Power Supply Terminals Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power supply terminals. TERMINAL EXTERNAL EXTERNAL PIN STRAPPING PIN STRAPPING DESCRIPTION DESCRIPTION INPUT INPUT TYPE COMPONENTS (IF UNUSED) NAME NUMBER N12, U14, AGND Analog circuit ground terminals...

  • Page 41: Pc Card Power Switch Terminals

    Table 2−5. PC Card Power Switch Terminals Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals. TERMINAL EXTERNAL EXTERNAL DESCRIPTION DESCRIPTION INPUT INPUT OUTPUT OUTPUT TYPE COMPONENTS NAME Power switch clock. Information on the DATA line is sampled at the rising edge of PCMCIA power CLOCK CLOCK.

  • Page 42: Pci Address And Data Terminals

    Table 2−7. PCI Address and Data Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals. TERMINAL POWER POWER DESCRIPTION INPUT OUTPUT DESCRIPTION INPUT OUTPUT TYPE RAIL NAME AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24...

  • Page 43: Pci Interface Control Terminals

    Table 2−8. PCI Interface Control Terminals Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals. TERMINAL POWER POWER EXTERNAL EXTERNAL DESCRIPTION INPUT OUTPUT DESCRIPTION INPUT OUTPUT TYPE RAIL COMPONENTS NAME PCI device select. The controller asserts DEVSEL to claim a PCI cycle Pullup resistor per as the target device.

  • Page 44: Multifunction And Miscellaneous Terminals

    Table 2−9. Multifunction and Miscellaneous Terminals The power rail designation is not applicable for the multifunction and miscellaneous terminals. TERMINAL EXTERNAL EXTERNAL PIN STRAPPING PIN STRAPPING DESCRIPTION DESCRIPTION INPUT INPUT OUTPUT OUTPUT TYPE COMPONENTS (IF UNUSED) NAME USB enable. These output terminals control an A_USB_EN external CBT switch for each socket when an USB LVCO1...

  • Page 45: Bit Pc Card Address And Data Terminals

    Table 2−10. 16-Bit PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Card address and data terminal is unused, then the terminal may be left floating. SOCKET B TERMINAL †...

  • Page 46: Bit Pc Card Interface Control Terminals

    Table 2−11. 16-Bit PC Card Interface Control Terminals External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card interface control terminal is unused, then the terminal may be left floating. SKT B TERMINAL † SKT A TERMINAL POWER POWER...
  • Page 47 Table 2−11. 16-Bit PC Card Interface Control Terminals (Continued) SKT B TERMINAL † SKT A TERMINAL POWER POWER DESCRIPTION DESCRIPTION TYPE RAIL NAME NAME Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host memory read cycles. V CCA / A_OE B_OE...

  • Page 48: Cardbus Pc Card Interface System Terminals

    Table 2−12. CardBus PC Card Interface System Terminals A 33-Ω to 47-Ω series damping resistor (per PC Card specification) is the only external component needed for terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then the terminal may be left floating.

  • Page 49: Cardbus Pc Card Address And Data Terminals

    Table 2−13. CardBus PC Card Address and Data Terminals External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card address and data terminal is unused, then the terminal may be left floating. SKT B TERMINAL †...

  • Page 50: Cardbus Pc Card Interface Control Terminals

    Table 2−14. CardBus PC Card Interface Control Terminals If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating. SKT B TERMINAL † SKT A TERMINAL POWER POWER DESCRIPTION INPUT OUTPUT DESCRIPTION INPUT OUTPUT TYPE RAIL NAME...
  • Page 51 Table 2−14. CardBus PC Card Interface Control Terminals (Continued) SKT B TERMINAL † SKT A TERMINAL POWER POWER DESCRIPTION DESCRIPTION INPUT INPUT OUTPUT OUTPUT TYPE RAIL NAME NAME CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus V CCA / PCII4 PCIO4...

  • Page 52: Ieee 1394 Physical Layer Terminals

    Table 2−15. IEEE 1394 Physical Layer Terminals TERMINAL EXTERNAL EXTERNAL PIN STRAPPING PIN STRAPPING DESCRIPTION DESCRIPTION INPUT INPUT OUTPUT OUTPUT TYPE COMPONENTS (IF USED) NAME Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage. If it is not used, then this terminal must be strapped either to DVDD or GND through a resistor.

  • Page 53: Sd/Mmc Terminals

    Table 2−16. SD/MMC Terminals If any SD/MMC terminal is unused, then the terminal may be left floating. TERMINAL POWER POWER EXTERNAL EXTERNAL DESCRIPTION INPUT OUTPUT DESCRIPTION INPUT OUTPUT TYPE RAIL COMPONENTS NAME Power switch or MC_PWR_CTRL_0 Media card power control for flash media sockets. LVCO1 FET to turn power MC_PWR_CTRL_1...

  • Page 54: Smart Media/Xd Terminals

    Table 2−18. Smart Media/XD Terminals If any Smart Media/XD terminal is unused, then the terminal may be left floating. TERMINAL POWER POWER EXTERNAL EXTERNAL DESCRIPTION INPUT OUTPUT DESCRIPTION INPUT OUTPUT TYPE RAIL PARTS NAME Power switch or MC_PWR_CTRL_0 Media card power control for flash media sockets. LVCO1 FET to turn power MC_PWR_CTRL_1...

  • Page 55: Smart Card Terminals

    † Table 2−19. Smart Card Terminals If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be connected to 5 V. TERMINAL POWER POWER EXTERNAL EXTERNAL DESCRIPTION DESCRIPTION INPUT INPUT OUTPUT OUTPUT TYPE RAIL...
  • Page 56 2−30...

  • Page 57: Feature/Protocol Descriptions

    3 Feature/Protocol Descriptions The following sections give an overview of the PCI7x21/PCI7x11 controller. Figure 3−1 shows the connections to the PCI7x21/PCI7x11 controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. PCI Bus EEPROM SD/MMC...

  • Page 58: I/O Characteristics

    3.2 I/O Characteristics The PCI7x21/PCI7x11 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local Bus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 14.2, Recommended Operating Conditions, provides the electrical characteristics of the inputs and outputs. V CCP Tied for Open Drain Figure 3−2.

  • Page 59: Device Resets

    3.4.2 Device Resets The following are the requirements for proper reset of the PCI7x21/PCI7x11 controller: 1. GRST and PRST must both be asserted at power on. 2. GRST must be asserted for at least 2 ms at power on 3. PRST must be deasserted either at the same time or after GRST is asserted 4.

  • Page 60: Functions 0 And 1 (Cardbus) Subsystem Identification

    as bus master, by reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI offset B3h, see Section 4.50) causes the PCI7x21/PCI7x11 controller to route the SDA and SCL signals to the SDA and SCL terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h;...

  • Page 61: Function 2 (Ohci 1394) Subsystem Identification

    3.4.5 Function 2 (OHCI 1394) Subsystem Identification The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25, Subsystem Access Register).

  • Page 62: Pc Card Insertion/Removal And Recognition

    3.5.1 PC Card Insertion/Removal and Recognition The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined. The scheme uses the card-detect and voltage-sense signals.

  • Page 63: Flash Media Card Detection

    Table 3−2. PC Card—Card Detect and Voltage Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Interface V CC V PP /V CORE Ground Ground Open Open 16-bit PC Card Per CIS (V PP ) Ground Ground Open Ground 16-bit PC Card 5 V and 3.3 V Per CIS (V PP ) 5 V, 3.3 V, and Per CIS (V PP )

  • Page 64: Power Switch Interface

    3.5.5 Power Switch Interface The power switch interface of the PCI7x21/PCI7x11 controller is a 3-pin serial interface. This 3-pin interface is implemented such that the PCI7x21/PCI7x11 controller can connect to both the TPS2226 and TPS2228 power switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.31) selects the power switch that is implemented.

  • Page 65: Integrated Pullup Resistors For Pc Card Interface

    3.5.7 Integrated Pullup Resistors for PC Card Interface The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card configurations. The PCI7x21/PCI7x11 controller has integrated all of these pullup resistors and requires no additional external components.

  • Page 66: Cardbus Socket Registers

    Current Limiting R ≈ 150 Ω MFUNCx Current Limiting PCI7x21/ Socket A R ≈ 150 Ω PCI7x11 MFUNCy Socket B Figure 3−6. Two Sample LED Circuits As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.

  • Page 67: Serial Eeprom Interface

    • Frequency stability (overtemperature and age): A crystal with ±30 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm.

  • Page 68: Serial-Bus Start/Stop Conditions And Bit Transfers

    Start Stop Change of Condition Condition Data Allowed Data Line Stable, Data Valid Figure 3−7. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited;...

  • Page 69: Serial-Bus Eeprom Application

    Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command bit must be set to 1 to indicate a read-data transfer. In addition, the PCI7x21/PCI7x11 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers.

  • Page 70: Eeprom Loading Map

    Table 3−9. EEPROM Loading Map SERIAL ROM BYTE DESCRIPTION OFFSET CardBus function indicator (00h) Number of bytes (20h) PCI 04h, command register, function 0, bits 8, 6−5, 2−0 [4:3] Command Command Command RSVD Command Command Command register, bit 8 register, bit 6 register, bit 5 register, bit 2 register, bit 1...
  • Page 71 Table 3−9. EEPROM Loading Map (Continued) SERIAL ROM BYTE DESCRIPTION OFFSET PCI 2Ch, subsystem vendor ID, byte 0 PCI 2Dh, subsystem vendor ID, byte 1 PCI 2Eh, subsystem ID, byte 0 PCI 2Fh, subsystem ID, byte 1 PCI F4h, Link_Enh, byte 0, bits 7, 2, 1 OHCI 50h, host controller control, bit 23 [5:3] Link_Enh.

  • Page 72: Programmable Interrupt Subsystem

    Table 3−9. EEPROM Loading Map (Continued) SERIAL ROM BYTE DESCRIPTION OFFSET PCI 94h, slot 0 3.3 V maximum current PCI 98h, slot 1 3.3 V maximum current PCI 9Ch, slot 2 3.3 V maximum current Reserved (PCI A0h, slot 3 3.3 V maximum current) Reserved (PCI A4h, slot 4 3.3 V maximum current) Reserved (PCI A8h, slot 5 3.3 V maximum current) PCI Smart Card function indicator (05h)

  • Page 73: Pc Card Functional And Card Status Change Interrupts

    3.7.1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards.

  • Page 74: Interrupt Masks And Flags

    Table 3−11. PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION A transition on BVD1 indicates a change in the BVD1(STSCHG)//CSTSCHG PC Card battery conditions. Battery conditions Battery conditions (BVD1, BVD2) A transition on BVD2 indicates a change in the BVD2(SPKR)//CAUDIO 16-bit PC Card battery conditions.

  • Page 75: Using Parallel Irq Interrupts

    Table 3−10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register.

  • Page 76: Using Serialized Irqser Interrupts

    The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh, see Section 4.24). Table 3−12 summarizes the interrupt signaling modes. Table 3−12. Interrupt Pin Register Cross Reference INTPIN INTPIN INTPIN INTPIN INTPIN INTPIN...

  • Page 77: Power Management (Function 2)

    • Ring indicate • PCI power management • Cardbus bridge power management • ACPI support PCI Bus EEPROM SD/MMC Power Switch MS/MSPRO PCI7x21/P SM/xD CI7x11 Power Switch SD/MMC 1394a Socket Power Switch Card/ Card/ UltraMedia UltraMedia Card Card † The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCI7x21/PCI7x11 controller. PRST must be asserted for subsequent warm resets.

  • Page 78: Integrated Low-Dropout Voltage Regulator (Ldo-Vr)

    3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) The PCI7x21/PCI7x11 controller requires 1.5-V core voltage. The core power can be supplied by the PCI7x21/PCI7x11 controller itself using the internal LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal. Table 3−14 lists the requirements for both the internal core power supply and the external core power supply.

  • Page 79: Bit Pc Card Power Management

    3.8.5 16-Bit PC Card Power Management The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bit PC Card power management.

  • Page 80: Ring Indicate

    places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the PCI7x21/PCI7x11 controller when SUSPEND is asserted because the outputs are in a high-impedance state.

  • Page 81: Pci Power Management

    3.8.9 PCI Power Management 3.8.9.1 CardBus Power Management (Functions 0 and 1) The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus.

  • Page 82: Ohci 1394 (Function 2 Power Management

    For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges. 3.8.9.2 OHCI 1394 (Function 2) Power Management The PCI7x21/PCI7x11 controller complies with the PCI Bus Power Management Interface Specification. The controller supports the D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power management definition in the 1394 Open Host Controller Interface Specification, Appendix A4.

  • Page 83: Acpi Support

    The Texas Instruments PCI7x21/PCI7x11 controller addresses these D3 wake-up issues in the following manner: • Two resets are provided to handle preservation of PME context bits: − Global reset (GRST) is used only on the initial boot up of the system after power up. It places the PCI7x21/PCI7x11 controller in its default state and requires BIOS to configure the controller before becoming fully functional.
  • Page 84 • ExCA card status-change interrupt configuration register (ExCA 805h/845h, see Section 5.6): bits 3−0 • ExCA card detect and general control register (ExCA 816h/856h, see Section 5.19): bits 7, 6 • Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0 •...
  • Page 85 The global reset-only (function 3) register bits: • Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15–0 • Subsystem ID register (PCI offset 2Eh, see Section 11.10): bits 15–0 • Power management control and status register (PCI offset 48h, see Section 11.18): bits 15, 8, 1, 0 •...

  • Page 86: Ieee 1394 Application Information

    3.9 IEEE 1394 Application Information 3.9.1 PHY Port Cable Connection PCI7x21/ 400 kΩ PCI7x11 Cable Power Pair 1 µF TPBIAS 56 Ω 56 Ω TPA+ Cable Pair TPA− Cable Port TPB+ Cable Pair TPB− 56 Ω 56 Ω 220 pF 5 kΩ...

  • Page 87: Crystal Selection

    Outer Cable Shield Chassis Ground Figure 3−19. Non-DC Isolated Outer Shield Termination 3.9.2 Crystal Selection The PCI7x21/PCI7x11 controller is designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates.

  • Page 88: Bus Reset

    C PHY + C BD 24.576 MHz Figure 3−20. Load Capacitance for the PCI7x21/PCI7x11 PHY The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors must be considered as a unit during layout.
  • Page 89 Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and Gap_Count in PHY register 1: • Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus.
  • Page 90 3−34...

  • Page 91: Pc Card Controller Programming Model

    4 PC Card Controller Programming Model This chapter describes the PCI7x21/PCI7x11 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI7x21/PCI7x11 function. There are some bits which affect both CardBus functions, but which, in order to work properly, must be accessed only through function 0. These are called global bits. Registers containing one or more global bits are denoted by §...

  • Page 92: Vendor Id Register

    § One or more bits in this register are global in nature and must be accessed only through function 0. 4.2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Name Vendor ID...

  • Page 93: Device Id Register Functions 0 And 1

    4.3 Device ID Register Functions 0 and 1 This read-only register contains the device ID assigned by TI to the PCI7x21/PCI7x11 CardBus controller functions (PCI functions 0 and 1). Name Device ID—Smart Card enabled Type Default Register: Device ID Offset: 02h (Functions 0 and 1) Type: Read-only...

  • Page 94: Command Register

    4.4 Command Register The PCI command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this register are shared among the PCI7x21/PCI7x11 PCI functions.

  • Page 95: Status Register

    Table 4−3. Command Register Description (continued) SIGNAL TYPE FUNCTION Memory space enable. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles in PCI memory space. MEM_EN 0 = Disables the PCI7x21/PCI7x11 response to memory space accesses (default) 1 = Enables the PCI7x21/PCI7x11 response to memory space accesses I/O space control.

  • Page 96: Revision Id Register

    Table 4−4. Status Register Description (continued) SIGNAL TYPE FUNCTION Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI CAPLIST capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function.

  • Page 97: Latency Timer Register

    4.9 Latency Timer Register The latency timer register specifies the latency timer for the PCI7x21/PCI7x11 controller, in units of PCI clock cycles. When the PCI7x21/PCI7x11 controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI7x21/PCI7x11 transaction has terminated, then the PCI7x21/PCI7x11 controller terminates the transaction when its GNT is deasserted.

  • Page 98: Cardbus Socket Registers/Exca Base Address Register

    4.12 CardBus Socket Registers/ExCA Base Address Register This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary.

  • Page 99: Secondary Status Register

    4.14 Secondary Status Register The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but is accessed on a per-socket basis.

  • Page 100: Pci Bus Number Register

    4.15 PCI Bus Number Register The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI7x21/PCI7x11 controller is connected. The PCI7x21/PCI7x11 controller uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

  • Page 101: Cardbus Latency Timer Register

    4.18 CardBus Latency Timer Register The CardBus latency timer register is programmed by the host system to specify the latency timer for the PCI7x21/PCI7x11 CardBus interface, in units of CCLK cycles. When the PCI7x21/PCI7x11 controller is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI7x21/PCI7x11 transaction has terminated, then the PCI7x21/PCI7x11 controller terminates the transaction at the end of the next data phase.

  • Page 102: Cardbus Memory Limit Registers 0, 1

    4.20 CardBus Memory Limit Registers 0, 1 These registers indicate the upper address of a PCI memory address range. They are used by the PCI7x21/PCI7x11 controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI.

  • Page 103: Cardbus I/O Limit Registers 0, 1

    4.22 CardBus I/O Limit Registers 0, 1 These registers indicate the upper address of a PCI I/O address range. They are used by the PCI7x21/PCI7x11 controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI.

  • Page 104: Interrupt Pin Register

    4.24 Interrupt Pin Register The value read from this register is function dependent. The default value for function 0 is 01h (INTA), the default value for function 1 is 02h (INTB), the default value for function 2 is 03h (INTC), the default value for function 3 is 01h (INTA), the default value for function 4 is 01h (INTA), the default value for function 5 is 01h (INTA).

  • Page 105: Type

    Register: Interrupt pin Offset: Type: Read-only Default: 01h (function 0), 02h (function 1), 03h (function 2), 04h (function 3), 04h (function 4), 04h (function 5) Table 4−6. Interrupt Pin Register Cross Reference INTRTIE BIT TIEALL BIT INTPIN INTPIN INTPIN INTPIN INTPIN INTPIN (BIT 29,...

  • Page 106: Subsystem Vendor Id Register

    Table 4−7. Bridge Control Register Description (Continued) SIGNAL TYPE FUNCTION CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal can also be asserted by passing a PRST assertion to CardBus. 0 = CRST is deasserted.

  • Page 107: Subsystem Id Register

    4.27 Subsystem ID Register The subsystem ID register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only.

  • Page 108: System Control Register

    4.29 System Control Register System-level initializations are performed through programming this doubleword register. Some of the bits are global in nature and must be accessed only through function 0. See Table 4−8 for a complete description of the register contents. Name System control Type...
  • Page 109 Table 4−8 System Control Register Description (continued) SIGNAL TYPE FUNCTION CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven low when a CardBus card has been inserted. When this bit is low, these signals are placed in a 22 ‡...

  • Page 110: Rw Rw Rw Rw

    Table 4−8 System Control Register Description (continued) SIGNAL TYPE FUNCTION CardBus data parity SERR signaling enable. 4 ‡§ CB_DPAR 0 = CardBus data parity not signaled on PCI SERR signal (default) 1 = CardBus data parity signaled on PCI SERR signal 3 ‡§...

  • Page 111: General Control Register

    4.31 General Control Register The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394 OHCI function and provides control over miscellaneous new functionality. See Table 4−9 for a complete description of the register contents. Name General control Type...

  • Page 112: General Control Register Description

    Table 4−9. General Control Register Description SIGNAL TYPE FUNCTION Flash media power control pin polarity. This bit controls the polarity of the MC_PWR_CTRL_0 and FM_PWR_CTRL MC_PWR_CTRL_1 terminals. 15 ‡ _POL 0 = MC_PWR_CTRL_x terminals are active low (default) 1 = MC_PWR_CTRL_x terminals are active high Smart Card interface select.

  • Page 113: General-Purpose Event Status Register

    4.32 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when general events occur, and can be programmed to generate general-purpose event signaling through GPE. See Table 4−10 for a complete description of the register contents. Name General-purpose event status Type...

  • Page 114: General-Purpose Event Enable Register

    4.33 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−11 for a complete description of the register contents. Name General-purpose event enable Type Default Register: General-purpose event enable Offset: Type: Read-only, Read/Write...

  • Page 115: General-Purpose Output Register

    4.35 General-Purpose Output Register The general-purpose output register is used to drive the GPO4−GPO0 outputs. See Table 4−13 for a complete description of the register contents. Name General-purpose output Type Default Register: General-purpose output Offset: Type: Read-only, Read/Write Default: Table 4−13. General-Purpose Output Register Description SIGNAL TYPE FUNCTION...

  • Page 116: Multifunction Routing Status Register

    4.36 Multifunction Routing Status Register The multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These terminals may be configured for various functions. This register is intended to be programmed once at power-on initialization. The default value for this register can also be loaded through a serial EEPROM. See Table 4−14 for a complete description of the register contents.

  • Page 117: Retry Status Register

    Table 4−14. Multifunction Routing Status Register Description (Continued) SIGNAL TYPE FUNCTION Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: 0000 = GPI1 0100 = OHCI_LED 1000 = CAUDPWM 1100 = LEDA1 7−4 ‡...

  • Page 118: Card Control Register

    4.38 Card Control Register The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the enable bit is shared between functions 0 and 1. See Table 4−16 for a complete description of the register contents. The RI_OUT signal is enabled through this register, and the enable bit is shared between functions 0 and 1.

  • Page 119: Device Control Register

    4.39 Device Control Register The device control register is provided for PCI1130 compatibility. It contains bits that are shared between functions 0 and 1. The interrupt mode select is programmed through this register. The socket-capable force bits are also programmed through this register. See Table 4−17 for a complete description of the register contents. Name Device control Type...

  • Page 120: Diagnostic Register

    4.40 Diagnostic Register The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written to it. See Table 4−18 for a complete description of the register contents. Name Diagnostic Type Default Register: Diagnostic...

  • Page 121: Capability Id Register

    4.41 Capability ID Register The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value.

  • Page 122: Power Management Capabilities Register

    4.43 Power Management Capabilities Register The power management capabilities register contains information on the capabilities of the PC Card function related to power management. Both PCI7x21/PCI7x11 CardBus bridge functions support D0, D1, D2, and D3 power states. Default register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification revision 1.1.

  • Page 123: Power Management Control/Status Register

    4.44 Power Management Control/Status Register The power management control/status register determines and changes the current power state of the PCI7x21/PCI7x11 CardBus function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3 to D0 state.

  • Page 124: Power Management Control/Status Bridge Support Extensions Register

    4.45 Power Management Control/Status Bridge Support Extensions Register This register supports PCI bridge-specific functionality. It is required for all PCI-to-PCI bridges. See Table 4−21 for a complete description of the register contents. Name Power management control/status bridge support extensions Type Default Register: Power management control/status bridge support extensions...

  • Page 125: Serial Bus Data Register

    4.47 Serial Bus Data Register The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial bus slave address must be programmed with the 7-bit slave address, and the read/write indicator bit must be reset.

  • Page 126: Default

    4.49 Serial Bus Slave Address Register The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit.

  • Page 127: Serial Bus Control/Status Register

    4.50 Serial Bus Control/Status Register The serial bus control and status register communicates serial bus status information and selects the quick command protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register.
  • Page 128 4−38...

  • Page 129: Exca Compatibility Registers (Functions 0 And 1)

    5 ExCA Compatibility Registers (Functions 0 and 1) The ExCA (exchangeable card architecture) registers implemented in the PCI7x21/PCI7x11 controller are register-compatible with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base), and reading or writing the data register (I/O base + 1).

  • Page 130: Exca Register Access Through I/O

    Host I/O Space Offset PCI7x21/PCI7x11 Configuration Registers Offset PC Card A ExCA Registers CardBus Socket/ExCA Base Address Index Data 16-Bit Legacy-Mode Base Address PC Card B ExCA Registers Note: The 16-bit legacy-mode base address register is shared by function 0 and 1 as indicated by the shading.

  • Page 131: Exca Registers And Offsets

    Table 5−1. ExCA Registers and Offsets PCI MEMORY ADDRESS EXCA OFFSET EXCA OFFSET EXCA REGISTER NAME OFFSET (HEX) (CARD A) (CARD B) Identification and revision ‡ Interface status Power control † 802† Interrupt and general control † 803† Card status change † 804†...
  • Page 132 Table 5−1. ExCA Registers and Offsets (continued) PCI MEMORY ADDRESS EXCA OFFSET EXCA OFFSET EXCA REGISTER NAME OFFSET (HEX) (CARD A) (CARD B) Reserved Reserved Memory window 3 start-address low-byte Memory window 3 start-address high-byte Memory window 3 end-address low-byte Memory window 3 end-address high-byte Memory window 3 offset-address low-byte Memory window 3 offset-address high-byte...

  • Page 133: Exca Identification And Revision Register

    5.1 ExCA Identification and Revision Register This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. See Table 5−2 for a complete description of the register contents. NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only. Name ExCA identification and revision Type...

  • Page 134: Exca Interface Status Register

    5.2 ExCA Interface Status Register This register provides information on current status of the PC Card interface. An X in the default bit values indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a complete description of the register contents.

  • Page 135: Exca Power Control Register

    5.3 ExCA Power Control Register This register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 5−5 for a complete description of the register contents.

  • Page 136: Exca Interrupt And General Control Register

    5.4 ExCA Interrupt and General Control Register This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See Table 5−6 for a complete description of the register contents. Name ExCA interrupt and general control Type Default Register:...

  • Page 137: Exca Card Status-Change Register

    5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0.

  • Page 138: Exca Card Status-Change Interrupt Configuration Register

    5.6 ExCA Card Status-Change Interrupt Configuration Register This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. See Table 5−8 for a complete description of the register contents. Name ExCA card status-change interrupt configuration Type Default Register: ExCA card status-change interrupt configuration...

  • Page 139: Exca Address Window Enable Register

    5.7 ExCA Address Window Enable Register The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI7x21/PCI7x11 controller does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers.

  • Page 140: Exca I/O Window Control Register

    5.8 ExCA I/O Window Control Register The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See Table 5−10 for a complete description of the register contents. Name ExCA I/O window control Type Default Register: ExCA /O window control...

  • Page 141: Exca I/O Windows 0 And 1 Start-Address Low-Byte Registers

    5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. Name ExCA I/O windows 0 and 1 start-address low-byte Type...

  • Page 142: Exca I/O Windows 0 And 1 End-Address Low-Byte Registers

    5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. Name ExCA I/O windows 0 and 1 end-address low-byte Type...

  • Page 143: Exca Memory Windows 0−4 Start-Address Low-Byte Registers

    5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the start address. Name ExCA memory windows 0−4 start-address low-byte Type...

  • Page 144: Exca Memory Windows 0−4 Start-Address High-Byte Registers

    5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory window data width and wait states are set in this register.

  • Page 145: Exca Memory Windows 0−4 End-Address Low-Byte Registers

    5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the end address. Name ExCA memory windows 0−4 end-address low-byte Type...

  • Page 146: Exca Memory Windows 0−4 End-Address High-Byte Registers

    5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory window wait states are set in this register.

  • Page 147: Exca Memory Windows 0−4 Offset-Address Low-Byte Registers

    5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address. Name ExCA memory windows 0−4 offset-address low-byte Type...

  • Page 148: Exca Memory Windows 0−4 Offset-Address High-Byte Registers

    5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register.

  • Page 149: Exca Card Detect And General Control Register

    5.19 ExCA Card Detect and General Control Register This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the VS1 and VS2 signals at the PC Card interface. Table 5−14 describes each bit in the ExCA card detect and general control register.

  • Page 150: Exca Global Control Register

    5.20 ExCA Global Control Register This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in this register are retained for 82365SL-DF compatibility. See Table 5−15 for a complete description of the register contents.

  • Page 151: Exca I/O Windows 0 And 1 Offset-Address Low-Byte Registers

    5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. Name ExCA I/O windows 0 and 1 offset-address low-byte Type...

  • Page 152: Exca Memory Windows 0−4 Page Registers

    5.23 ExCA Memory Windows 0−4 Page Registers The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16-Mbyte regions in the 4-gigabyte PCI address space.

  • Page 153: Accessing Cardbus Socket Registers Through Pci Memory

    6 CardBus Socket Registers (Functions 0 and 1) The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI7x21/PCI7x11 controller provides the CardBus socket/ExCA base address register (PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Each function has a separate base address register for accessing the CardBus socket registers (see Figure 6−1).

  • Page 154: Socket Event Register

    6.1 Socket Event Register This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit.

  • Page 155: Socket Mask Register

    6.2 Socket Mask Register This register allows software to control the CardBus card events which generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see Section 6.1).

  • Page 156: Socket Present State Register

    6.3 Socket Present State Register This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card V support and card type is only updated at each insertion.

  • Page 157: Socket Force Event Register

    Table 6−4. Socket Present State Register Description (Continued) SIGNAL TYPE FUNCTION Bad V CC request. This bit indicates that the host software has requested that the socket be powered at an invalid voltage. 9 † BADVCCREQ 0 = Normal operation (default) 1 = Invalid V CC request by host software Data lost.

  • Page 158: Socket Force Event Register Description

    Table 6−5. Socket Force Event Register Description SIGNAL TYPE FUNCTION 31−15 RSVD Reserved. These bits return 0s when read. Card VS test. When this bit is set, the PCI7x21/PCI7x11 controller reinterrogates the PC Card, updates CVSTEST the socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control. Force YV card.

  • Page 159: Socket Control Register

    6.5 Socket Control Register This register provides control of the voltages applied to the socket V and V . The PCI7x21/PCI7x11 controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6−6 for a complete description of the register contents.

  • Page 160: Socket Power Management Register

    6.6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents. Name Socket power management Type...

  • Page 161: Ohci Controller Programming Model

    7 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 1394 open host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.

  • Page 162: Device Id Register

    Vendor ID Offset: Type: Read-only Default: 104Ch 7.2 Device ID Register The device ID register contains a value assigned to the PCI7x21/PCI7x11 controller by Texas Instruments. The device identification for the PCI7x21/PCI7x11 controller is 8032h. Name Device ID Type Default Register:...

  • Page 163: Register: Command

    7.3 Command Register The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−2 for a complete description of the register contents.

  • Page 164: Status Register Description

    7.4 Status Register The status register provides status over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−3 for a complete description of the register contents.

  • Page 165: Class Code And Revision Id Register

    7.5 Class Code and Revision ID Register The class code and revision ID register categorizes the PCI7x21/PCI7x11 controller as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte.

  • Page 166: Header Type And Bist Register

    7.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the PCI7x21/PCI7x11 PCI header type and no built-in self-test. See Table 7−6 for a complete description of the register contents. Name Header type and BIST Type Default Register:...

  • Page 167: Ti Extension Base Address Register

    7.9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers.

  • Page 168: Cardbus Cis Base Address Register

    7.10 CardBus CIS Base Address Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read. See Table 7−9 for a complete description of the register contents. Name CardBus CIS base address Type Default Name...

  • Page 169: Subsystem Identification Register

    7.12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25). See Table 7−10 for a complete description of the register contents. Name Subsystem identification Type...

  • Page 170: Interrupt Line Register

    7.14 Interrupt Line Register The interrupt line register communicates interrupt line routing information. See Table 7−11 for a complete description of the register contents. Name Interrupt line Type Default Register: Interrupt line Offset: Type: Read/Write Default: Table 7−11. Interrupt Line Register Description FIELD NAME TYPE DESCRIPTION...

  • Page 171: Minimum Grant And Maximum Latency Register

    7.16 Minimum Grant and Maximum Latency Register The minimum grant and maximum latency register communicates to the system the desired setting of bits 15−8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST.

  • Page 172: Capability Id And Next Item Pointer Registers

    7.18 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 7−15 for a complete description of the register contents. Name Capability ID and next item pointer Type...

  • Page 173: Power Management Capabilities Register Description

    7.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the PCI7x21/PCI7x11 controller related to PCI power management. See Table 7−16 for a complete description of the register contents. Name Power management capabilities Type Default Register: Power management capabilities Offset: Type:...

  • Page 174: Power Management Control And Status Register

    7.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power-management function. This register is not affected by the internally generated reset caused by the transition from the D3 to D0 state.

  • Page 175: Pci Phy Control Register

    7.22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−19 for a complete description of the register contents. Name PCI PHY control Type Default Name PCI PHY control Type Default Register:...

  • Page 176: Pci Miscellaneous Configuration Register

    7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7−20 for a complete description of the register contents. Name PCI miscellaneous configuration Type Default Name PCI miscellaneous configuration Type Default Register: PCI miscellaneous configuration Offset: Type: Read/Write, Read-only...

  • Page 177: Link Enhancement Control Register

    Table 7−20. PCI Miscellaneous Configuration Register Description (Continued) FIELD NAME TYPE DESCRIPTION DISABLE_ When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature 1 ‡ PCIGATE only and must be cleared to 0 (all applications). When bit 0 is set to 1, the PCI clock is always kept running through the CLKRUN protocol.

  • Page 178: Subsystem Access Register

    Table 7−21. Link Enhancement Control Register Description (Continued) FIELD NAME TYPE DESCRIPTION RSVD Reserved. Bit 11 returns 0 when read. Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled for 10 ‡ enab_mpeg_ts MPEG CIP transmit streams (FMT = 20h).

  • Page 179: Gpio Control Register

    7.26 GPIO Control Register The GPIO control register has the control and status bits for GPIO0, GPIO1, GPIO2, and GPIO3 ports. Upon reset, GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively. The BMC terminal can be configured as GPIO0 by setting bit 7 (DISABLE_BMC) to 1.
  • Page 180 Table 7−23. GPIO Control Register Description (Continued) SIGNAL TYPE FUNCTION GPIO1 enable control. When bit 15 (DISABLE_LPS) is set to 1, this bit controls the output enable for GPIO1. GPIO_ENB1 0 = High-impedance output (default) 1 = Output is enabled 11−9 RSVD Reserved.

  • Page 181: Ohci Registers

    8 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the PCI7x21/PCI7x11 IEEE 1394 link function. This section provides the register interface and bit descriptions.
  • Page 182 Table 8−1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET Self-ID Reserved — Self-ID buffer pointer SelfIDBuffer Self-ID count SelfIDCount Reserved — — IRChannelMaskHiSet Isochronous receive channel mask high Isochronous receive channel mask high IRChannelMaskHiClear IRChannelMaskLoSet Isochronous receive channel mask low Isochronous receive channel mask low IRChannelMaskLoClear IntEventSet...
  • Page 183 Table 8−1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET ContextControlSet 180h Asynchronous context control Asynchronous context control ContextControlClear 184h Asynchronous Asynchronous Request Transmit Request Transmit Reserved — 188h [ ATRQ ] [ ATRQ ] Asynchronous context command pointer CommandPtr 18Ch Reserved...

  • Page 184: Ohci Version Register

    8.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 8−2 for a complete description of the register contents. Name OHCI version Type Default Name OHCI version Type Default Register:...

  • Page 185: Guid Rom Register

    8.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1. See Table 8−3 for a complete description of the register contents.

  • Page 186: Asynchronous Transmit Retries Register

    8.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the PCI7x21/PCI7x11 controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 8−4 for a complete description of the register contents. Name Asynchronous transmit retries Type...

  • Page 187: Csr Compare Register

    8.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. Name CSR compare Type Default Name CSR compare...

  • Page 188: Configuration Rom Header Register

    8.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 8−6 for a complete description of the register contents. Name Configuration ROM header Type Default Name...

  • Page 189: Bus Options Register

    8.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a complete description of the register contents. Name Bus options Type Default Name Bus options Type Default Register: Bus options Offset: Type: Read/Write, Read-only...

  • Page 190: Guid High Register

    8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST.

  • Page 191: Configuration Rom Mapping Register

    8.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 8−8 for a complete description of the register contents. Name Configuration ROM mapping Type...

  • Page 192: Posted Write Address High Register

    8.15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The PCI7x21/PCI7x11 controller implements Texas Instruments unique behavior with regards to OHCI. Thus, this register is read-only and returns 0108 0028h when read.

  • Page 193: Host Controller Control Register

    8.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the PCI7x21/PCI7x11 controller. See Table 8−11 for a complete description of the register contents. Name Host controller control Type RSCU Default Name Host controller control Type Default Register:...

  • Page 194: Self-Id Buffer Pointer Register

    Table 8−11. Host Controller Control Register Description (Continued) FIELD NAME TYPE DESCRIPTION aPhyEnhanceEnable When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to 1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0, the software does not change PHY enhancements or this bit.

  • Page 195: Self-Id Count Register

    8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete description of the register contents.

  • Page 196: Isochronous Receive Channel Mask High Register

    8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register.

  • Page 197: Isochronous Receive Channel Mask Low Register

    Table 8−13. Isochronous Receive Channel Mask High Register Description (Continued) FIELD NAME TYPE DESCRIPTION isoChannel38 When bit 6 is set to 1, the controller is enabled to receive from isochronous channel number 38. isoChannel37 When bit 5 is set to 1, the controller is enabled to receive from isochronous channel number 37. isoChannel36 When bit 4 is set to 1, the controller is enabled to receive from isochronous channel number 36.

  • Page 198: Interrupt Event Register

    8.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various PCI7x21/PCI7x11 interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register.
  • Page 199 Table 8−15. Interrupt Event Register Description (Continued) FIELD NAME TYPE DESCRIPTION cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start.

  • Page 200: Interrupt Mask Register

    8.22 Interrupt Mask Register The interrupt mask set/clear register enables the various PCI7x21/PCI7x11 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 8−15.
  • Page 201 Table 8−16. Interrupt Mask Register Description (Continued) FIELD NAME TYPE DESCRIPTION regAccessFail When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this register-access-failed interrupt mask enables interrupt generation. busReset When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this bus-reset interrupt mask enables interrupt generation.

  • Page 202: Isochronous Transmit Interrupt Event Register

    8.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see Section 8.21), software can check this register to determine which context(s) caused the interrupt.

  • Page 203: Isochronous Transmit Interrupt Mask Register

    8.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register.

  • Page 204: Isochronous Receive Interrupt Event Register

    8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) has occurred, software can check this register to determine which context(s) caused the interrupt.

  • Page 205: Isochronous Receive Interrupt Mask Register

    8.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register.

  • Page 206: Initial Channels Available High Register

    8.28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8−20 for a complete description of the register contents. Name Initial channels available high Type...

  • Page 207: Fairness Control Register

    8.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 8−22 for a complete description of the register contents. Name Fairness control Type Default...

  • Page 208: Link Control Register

    8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the PCI7x21/PCI7x11 controller. It contains controls for the receiver and cycle timer. See Table 8−23 for a complete description of the register contents.

  • Page 209: Node Identification Register

    8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field (bits 5−0) is referred to as the node ID. See Table 8−24 for a complete description of the register contents.

  • Page 210: Phy Layer Control Register

    8.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register. See Table 8−25 for a complete description of the register contents. Name PHY layer control Type Default Name PHY layer control Type Default Register: PHY layer control...

  • Page 211: Isochronous Cycle Timer Register

    8.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the PCI7x21/PCI7x11 controller is cycle master, this register is transmitted with the cycle start message. When the PCI7x21/PCI7x11 controller is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.

  • Page 212: Asynchronous Request Filter High Register

    8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined.
  • Page 213 Table 8−27. Asynchronous Request Filter High Register Description (Continued) FIELD NAME TYPE DESCRIPTION asynReqResource50 If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the controller from that node are accepted. asynReqResource49 If bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the controller from that node are accepted.

  • Page 214: Asynchronous Request Filter Low Register

    8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 8−28 for a complete description of the register contents. Name Asynchronous request filter low Type...

  • Page 215: Physical Request Filter High Register

    8.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register.
  • Page 216 Table 8−29. Physical Request Filter High Register Description (Continued) FIELD NAME TYPE DESCRIPTION physReqResource50 If bit 18 is set to 1 for local bus node number 50, physical requests received by the controller from that node are handled through the physical request context. physReqResource49 If bit 17 is set to 1 for local bus node number 49, physical requests received by the controller from that node are handled through the physical request context.

  • Page 217: Physical Request Filter Low Register

    8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register.

  • Page 218: Asynchronous Context Control Register

    8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 8−31 for a complete description of the register contents. Name Asynchronous context control Type Default Name Asynchronous context control Type RSCU Default...

  • Page 219: Asynchronous Context Command Pointer Register

    8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x11 controller accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 8.40) to 1.

  • Page 220: Isochronous Transmit Context Control Register

    8.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7).

  • Page 221: Isochronous Transmit Context Command Pointer Register

    8.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x11 controller accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1. The isochronous transmit DMA context command pointer can be read when a context is active.
  • Page 222 Table 8−34. Isochronous Receive Context Control Register Description (Continued) FIELD NAME TYPE DESCRIPTION cycleMatchEnable RSCU When bit 29 is set to 1 and the 13-bit cycleMatch field (bits 24−12) in the isochronous receive context match register (See Section 8.46) matches the 13-bit cycleCount field in the cycleStart packet, the context begins running.

  • Page 223: Isochronous Receive Context Command Pointer Register

    8.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21/PCI7x11 controller accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 8.44) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).

  • Page 224: Isochronous Receive Context Match Register

    8.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).

  • Page 225: Ti Extension Registers

    9 TI Extension Registers The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 7.9, TI Extension Base Address Register, for register bit field details. See Table 9−1 for the TI extension register listing. Table 9−1.

  • Page 226: Isochronous Receive Digital Video Enhancements

    9.2 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1).
  • Page 227 Table 9−2. Isochronous Receive Digital Video Enhancements Register Description (Continued) FIELD NAME TYPE DESCRIPTION 7−6 RSVD Reserved. Bits 7 and 6 return 0s when read. DV_Branch1 When bit 5 is set to 1, the isochronous receive context 1 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place.

  • Page 228: Link Enhancement Register

    9.4 Link Enhancement Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below.

  • Page 229: Timestamp Offset Register

    Table 9−3. Link Enhancement Register Description (Continued) FIELD NAME TYPE DESCRIPTION RSVD Reserved. Bit 9 returns 0 when read. Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV 8 ‡ enab_dv_ts CIP transmit streams (FMT = 00h).
  • Page 230 9−6...

  • Page 231: Phy Register Configuration

    10 PHY Register Configuration There are 16 accessible internal registers in the PCI7x21/PCI7x11 controller. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected.

  • Page 232: Base Register Field Descriptions

    Table 10−2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. Root.
  • Page 233 Table 10−2. Base Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY layer to initiate a short (1.3 µs) ISBR arbitrated bus reset at the next opportunity. This bit is cleared to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus resets.

  • Page 234: Port Status Register

    10.2 Port Status Register The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 10−3 shows the configuration of the port status page registers and Table 10−4 shows the corresponding field descriptions.

  • Page 235: Vendor Identification Register

    Vendor_ID Manufacturer’s organizationally unique identifier (OUI). For the PCI7x21/PCI7x11 controller this field is 08 0028h (Texas Instruments) (the MSB is at register address 1010b). Product_ID Product identifier. For the PCI7x21/PCI7x11 controller this field is 42 4499h (the MSB is at register address 1101b).

  • Page 236: Vendor-Dependent Register

    10.4 Vendor-Dependent Register The vendor-dependent page provides access to the special control features of the PCI7x21/PCI7x11 controller, as well as to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10−7 shows the configuration of the vendor-dependent page, and Table 10−8 shows the corresponding field descriptions.

  • Page 237: Power-Class Programming

    10.5 Power-Class Programming The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted self-ID packet. Table 10−9 shows the descriptions of the various power classes. The default power-class value is loaded following a system (hardware) reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4.
  • Page 238 10−8...

  • Page 239: Flash Media Controller Programming Model

    11 Flash Media Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 flash media controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.

  • Page 240: Vendor Id Register

    Offset: Type: Read-only Default: 104Ch 11.2 Device ID Register The device ID register contains a value assigned to the flash media controller by Texas Instruments. The device identification for the flash media controller is 8033h. Name Device ID Type Default...

  • Page 241: Command Register

    11.3 Command Register The command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 11−2 for a complete description of the register contents.

  • Page 242: Status Register

    11.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location;...

  • Page 243: Latency Timer And Class Cache Line Size Register

    11.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 01h, identifying the controller as a mass storage controller. The subclass is 80h, identifying the function as other mass storage controller, and the programming interface is 00h.

  • Page 244: Flash Media Base Address Register

    11.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and no built-in self-test. See Table 11−6 for a complete description of the register contents. Name Header type and BIST Type Default Register:...

  • Page 245: Subsystem Vendor Identification Register

    11.9 Subsystem Vendor Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 50h (see Section 11.22). All bits in this register are reset by GRST only. Name Subsystem vendor identification Type...

  • Page 246: Pci Interrupt Pin Register

    11.12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the flash media interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function.

  • Page 247: Minimum Grant Register

    11.14 Minimum Grant Register The minimum grant register contains the minimum grant value for the flash media controller core. Name Minimum grant Type Default Register: Minimum grant Offset: Type: Read/Update Default: Table 11−9. Minimum Grant Register Description FIELD NAME TYPE DESCRIPTION Minimum grant.

  • Page 248: Capability Id And Next Item Pointer Registers Description

    11.16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 11−11 for a complete description of the register contents. Name Capability ID and next item pointer Type...

  • Page 249: Power Management Capabilities Register

    11.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the flash media controller related to PCI power management. See Table 11−12 for a complete description of the register contents. Name Power management capabilities Type Default Register: Power management capabilities Offset:...

  • Page 250: Power Management Bridge Support Extension Register

    11.18 Power Management Control and Status Register The power management control and status register implements the control and status of the flash media controller. This register is not affected by the internally generated reset caused by the transition from the D3 to D0 state.

  • Page 251: Power Management Data Register

    11.20 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the flash media controller; thus, it is read-only and returns 0 when read. Name Power management data Type Default Register: Power management data Offset: Type: Read-only...

  • Page 252: Subsystem Access Register Description

    11.22 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 11−15 for a complete description of the register contents. Name Subsystem access Type...

  • Page 253: Diagnostic Register Description

    11.23 Diagnostic Register This register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for M and N in this register set the PLL output to be 80 MHz, which is divided to get the 40 MHz and 20 MHz needed by the flash media cores.
  • Page 254 11−16...

  • Page 255: Sd Host Controller Programming Model

    12 SD Host Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 SD host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.

  • Page 256: Vendor Id Register

    Offset: Type: Read-only Default: 104Ch 12.2 Device ID Register The device ID register contains a value assigned to the SD host controller by Texas Instruments. The device identification for the SD host controller is 8034h. Name Device ID Type Default...

  • Page 257: Command Register

    12.3 Command Register The command register provides control over the SD host controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 12−2 for a complete description of the register contents.

  • Page 258: Status Register

    12.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location;...

  • Page 259: Class Code And Revision Id Register Description

    12.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h, identifying the function as an SD host controller.

  • Page 260: Latency Timer And Class Cache Line Size Register Description

    12.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the SD host controller. See Table 12−5 for a complete description of the register contents.

  • Page 261: Sd Host Base Address Register

    12.8 SD Host Base Address Register The SD host base address register specifies the base address of the memory-mapped interface registers for each standard SD host socket. The size of each base address register (BAR) is 256 bytes. The number of BARs is dependent on the number of SD sockets in the implementation See Table 12−7 for a complete description of the register contents.

  • Page 262: Capabilities Pointer Register

    12.10 Subsystem Identification Register The subsystem identification register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register are reset by GRST only. Name Subsystem identification Type...

  • Page 263: Minimum Grant Register Description

    12.13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 12−8, indicating that the SD host controller uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted.

  • Page 264: Maximum Latency Register

    12.15 Maximum Latency Register The maximum latency register contains the maximum latency value for the SD host controller core. Name Maximum latency Type Default Register: Maximum latency Offset: Type: Read/Update Default: Table 12−10. Maximum Latency Register Description FIELD NAME TYPE DESCRIPTION 7−0 MAX_LAT...

  • Page 265: Capability Id And Next Item Pointer Registers

    12.17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 12−12 for a complete description of the register contents. Name Capability ID and next item pointer Type...

  • Page 266: Power Management Capabilities Register

    12.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the SD host controller related to PCI power management. See Table 12−13 for a complete description of the register contents. Name Power management capabilities Type Default Register: Power management capabilities Offset:...

  • Page 267: Power Management Control And Status Register Description

    12.19 Power Management Control and Status Register The power management control and status register implements the control and status of the SD host controller. This register is not affected by the internally generated reset caused by the transition from the D3 to D0 state.

  • Page 268: Power Management Data Register

    12.21 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the SD host controller; thus, it is read-only and returns 0 when read. Name Power management data Type Default Register: Power management data Offset: Type: Read-only...

  • Page 269: Subsystem Access Register

    12.23 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 12−16 for a complete description of the register contents. Name Subsystem access Type...

  • Page 270: Slot 0 3.3-V Maximum Current Register

    12.25 Slot 0 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 0 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register.

  • Page 271: Slot 3 3.3-V Maximum Current Register

    12.28 Slot 3 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 3 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register.
  • Page 272 12−18...

  • Page 273: Smart Card Controller Programming Model

    13 Smart Card Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21/PCI7x11 Smart Card controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.

  • Page 274: Vendor Id Register

    Offset: Type: Read-only Default: 104Ch 13.2 Device ID Register The device ID register contains a value assigned to the Smart Card controller by Texas Instruments. The device identification for the Smart Card controller is 8035h. Name Device ID Type Default...

  • Page 275: Command Register

    13.3 Command Register The command register provides control over the Smart Card controller interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. The SERR_EN and PERR_EN enable bits in this register are internally wired-OR between other functions, and these control bits appear separately according to their software function.

  • Page 276: Status Register

    13.4 Status Register The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location;...

  • Page 277: Class Code And Revision Id Register

    13.5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class, subclass, and programming interface of the function. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifying the function as other mass storage controller, and the programming interface is 00h.

  • Page 278: Smart Card Base Address Register 0

    13.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and no built-in self-test. See Table 13−6 for a complete description of the register contents. Name Header type and BIST Type Default Register:...

  • Page 279: Smart Card Base Address Register 1−4

    13.9 Smart Card Base Address Register 1−4 Each socket has its own base address register. For example, a device supports three Smart Card sockets uses three base address registers, BA1 (socket 0), BA2 (socket 1) and BA3 (socket 2). These registers are used by this function to determine where to forward a memory transaction to the Smart Card Control and Communication Register sets.

  • Page 280: Subsystem Identification Register

    13.11 Subsystem Identification Register This register is read-update and can be modified through the subsystem ID alias register. This register has no effect to the functionality. Default value is 8035h. This default value complies with the WLP (Windows Logo Program) requirements without BIOS or EEPROM configuration.

  • Page 281: Interrupt Pin Register

    13.14 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 13−7, indicating that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted.

  • Page 282: Maximum Latency Register Description

    13.16 Maximum Latency Register The maximum latency register contains the maximum latency value for the Smart Card controller core. Name Maximum latency Type Default Register: Maximum latency Offset: Type: Read/Update Default: Table 13−9. Maximum Latency Register Description FIELD NAME TYPE DESCRIPTION 7−0 MAX_LAT...

  • Page 283: Power Management Capabilities Register

    13.18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the Smart Card controller related to PCI power management. See Table 13−11 for a complete description of the register contents. Name Power management capabilities Type Default Register: Power management capabilities Offset:...

  • Page 284: Power Management Control And Status Register

    13.19 Power Management Control and Status Register The power management control and status register implements the control and status of the Smart Card controller. This register is not affected by the internally generated reset caused by the transition from the D3 to D0 state.

  • Page 285: Power Management Data Register

    13.21 Power Management Data Register The power management bridge support extension register provides extended power-management features not applicable to the Smart Card controller; thus, it is read-only and returns 0 when read. Name Power management data Type Default Register: Power management data Offset: Type: Read-only...

  • Page 286: Subsystem Id Alias Register

    13.23 Subsystem ID Alias Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. See Table 13−14 for a complete description of the register contents. Name Subsystem ID alias Type...

  • Page 287: Smart Card Configuration 1 Register

    13.25 Smart Card Configuration 1 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information of this register can be read from the Smart Card configuration 1 alias register in the Smart Card global control register set.
  • Page 288 Table 13−15. Smart Card Configuration 1 Register Description FIELD NAME TYPE DESCRIPTION 31−28 SCRTCH_PAD Scratch pad CLASS_B_SKT3 Socket 3 Class B Smart Card support. Since socket 3 is not implemented in the controller, this bit is a read-only 0. CLASS_B_SKT2 Socket 2 Class B Smart Card support.

  • Page 289: Smart Card Configuration 2 Register

    13.26 Smart Card Configuration 2 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information of this register can be read from the Smart Card configuration 2 alias in the Smart Card global control register set. The software utilizes this information and adjusts the software and firmware behavior, if necessary.
  • Page 290 13−18...

  • Page 291: Electrical Characteristics

    14 Electrical Characteristics † 14.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range, VR_PORT ........... −0.2 V to 2.2 V AVDD .
  • Page 292 Recommended Operating Conditions (continued) OPERATION UNIT 3.3 V 0.5 V CCP V CCP PCI k PCI k V CCP 3.3 V CardBus 0.475 V CC(A/B) V CC(A/B) 3.3 V 16-bit V CC(A/B) PC Card PC Card High-level input High-level input V IH †...
  • Page 293 Recommended Operating Conditions (continued) OPERATION UNIT ±1.08 S100 operation ±0.5 S200 operation Receive input jitter Receive input jitter TPA, TPB cable inputs TPA, TPB cable inputs ±0.315 S400 operation ±0.8 S100 operation ±0.55 S200 operation Receive input skew Receive input skew Between TPA and TPB cable inputs Between TPA and TPB cable inputs ±0.5...

  • Page 294: Electrical Characteristics Over Recommended Operating Conditions

    14.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TERMINALS OPERATION TEST CONDITIONS UNIT 3.3 V I OH = −0.5 mA 0.9 V CC I OH = −2 mA 3.3 V CardBus I OH = −0.15 mA 0.9 V CC V OH V OH High-level output voltage...

  • Page 295: Electrical Characteristics Over Recommended Ranges Of Operating Conditions

    14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) 14.4.1 Device PARAMETER TEST CONDITION UNIT Power status threshold, CPS input † 400-kΩ resistor † V TH TPBIAS output voltage At rated I O current 1.665 2.015 µA Input current (PC0−PC2 inputs) V CC = 3.6 V †...

  • Page 296: Pci Clock/Reset Timing Requirements Over Recommended Ranges Of Supply Voltage And Operating Free-Air Temperature

    14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature ALTERNATE PARAMETER TEST CONDITIONS UNIT SYMBOL Cycle time, PCLK t cyc t w(H) Pulse duration (width), PCLK high t high t w(L) Pulse duration (width), PCLK low t low ∆v/∆t t r , t f...

  • Page 297: Mechanical Information

    Seating Plane 0,55 0,12 0,08 0,45 0,45 0,35 4145273-4/E 08/02 NOTES: B. All linear dimensions are in millimeters. C. This drawing is subject to change without notice. D. MicroStar BGA configuration. MicroStar BGA is a trademark of Texas Instruments. 15−1...
  • Page 298 15−2...
  • Page 299 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2005 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing PCI7411GHK ACTIVE Call TI Level-3-220C-168 HR PCI7411ZHK ACTIVE BGA MI Green (RoHS & Call TI Level-3-260C-168HRS CROSTA no Sb/Br) PCI7421GHK ACTIVE...

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