Chipset Overview - Supermicro Supero C2SBX User Manual

Chapter 1: Introduction
1-2

Chipset Overview

The Intel X38/X48 Chipset is specially designed for use with Intel® Core™2 Ex-
treme, Quad, or Duo processors in the LGA775 Land Grid Array Package and the
ICH9R-based workstations. It consists of three primary components: the Memory
Controller Hub (MCH), the I/O Controller Hub (ICH9R) and the PXH-V chip.
Memory Controller Hub (MCH)
The MCH (North Bridge) manages the data flow between the CPU interface (FSB),
the System Memory interface, the PCI-Express interface, and the I/O Controller
through the Direct Media Interface (DMI). The ICH9R (South Bridge) provides
a multitude of I/O related functions. The MCH supports one or two channels of
DDR2/DDR3 memory SDRAM and a dual PCI-Express x16 (2.0) external graph-
ics port.
Intel ICH9R System Features
The Intel 9th Generation I/O Controller Hub (ICH9R) supports various I/O related
functions and PCI devices. It provides the data buffering, interface arbitration and
bandwidth needed to maximize system interface efficiency and maintain peak per-
formance at the same time. The ICH9R supports PCI-Express ports compatible
with the PCI-Express Base Specification, Rev.1.1. It also supports SATA connec-
tions at generation 1 and 2 speeds and USB 2.0 ports.
Additionally, the ICH9R features an integrated High Definition Audio Controller to
support extreme multimedia applications, accommodating a variety of third-party
audio codecs. It also supports the Intel Matrix Storage Technology which provides
the user with a wide array of RAID options for data security and signal transmis-
sion efficiency. Furthermore, the ICH9R offers next generation client management
capability through the use of Intel Active Management Technology in conjunction
with the use of the most advanced Gigabit Ethernet controller. The Intel 82566
LAN controller supports a single compact Gigabit LAN port. The GLAN Controller
connects to the ICH via an Intel proprietary Serial GLAN connection link.
The Direct Media Interface (DMI)
Providing the high-speed, chip-to-chip connection between the MCH and ICH9R
is the Direct Media Interface (DMI). The DMI integrates advanced priority-based
servicing, allowing for concurrent traffic, true isochronous transfer capabilities and
permitting current as well as legacy software to function seamlessly.
(For more information regarding the X38/X48 chipset, please refer to Intel's web
site @ http://www.intel.com.)
1-11