Acer 390 Series Service Manual page 68

Supports the most flexible six 32-bit populated banks of DRAM for easy DRAM upgrade
Supports SIMM and DIMM
Synchronous/Pseudo Synchronous 25/30/33MHz 3.3V/5V tolerance PCI interface
Concurrent PCI architecture
PCI bus arbiter: five PCI masters and M1533/ M1543 (ISA Bridge) supported
6 DWords for CPU-to-PCI memory write posted buffers
Converts back-to-back CPU to PCI memory write to PCI burst cycle
38/22 Dwords for PCI-to-DRAM Write-posted/ Read-prefetching buffers
PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-back)
L1/L2 pipelined-snoop ahead for PCI-to-DRAM cycle
Supports PCI mechanism #1 only
Complies with PCI spec. 2.1 (N(32/16/8)+8 rule, passive release, fair arbitration)
Enhanced performance for Memory-Read-Line, Memory-Read-Multiple and Memory-write-
Invalidate PCI commands
Enhanced Power Management
ACPI support
PCI bus CLKRUN function
Dynamic Clock Stop
Power-on Suspend
Suspend to Disk
Suspend to DRAM
Self refresh during Suspend
328-pin (27mm x 27mm) BGA package
2-22 Service Guide