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Table 2-8
65555 Pin Functions
Ball
Pin Name
AD0
U2
AD1
T3
AD2
R4
AD3
T2
AD4
U1
AD5
R3
AD6
T1
AD7
AD8
R2
AD9
R1
AD10
P2
AD11
N3
AD12
P1
AD13
N2
AD14
M4
AD15
M3
AD16
AD17
N1
AD18
J1
AD19
J2
AD20
H1
AD21
J3
AD22
J4
AD23
H2
AD24
AD25
G1
AD26
H3
AD27
G3
AD28
F2
AD29
E1
AD30
F3
AD31
D1
E2
F4
E3
P3
C/BE0#
M2
C/BE1#
K3
C/BE2#
F1
C/BE3#
G2
IDSEL
Note:
All signals listed above are powered by BVCC and GND.
2-68
Type
Active
I/O
High
PCI Address/Data Bus
I/O
High
Address and data are multiplexed on the same
I/O
High
pins. A bus transaction consists of an address
I/O
High
phase followed by one or more data phases (both
I/O
High
read and write bursts are allowed by the bus
I/O
High
definition).
I/O
High
The address phase is the clock cycle in which
I/O
High
FRAME# is asserted (AD0-31 contain a 32-bit
I/O
High
physical address) For l/O, the address is a byte
I/O
High
address. For memory and configuration, the
I/O
High
address is a DWORD address. During data
I/O
High
phases AD0-7 contain the LSB and 24-31 contain
I/O
High
the MSB. Write data is stable and valid when
I/O
High
IRDY# is asserted; read data is stable and valid
I/O
High
when TRDY# is asserted. Data transfers only
I/O
High
during those clocks when both IRDY# and
I/O
High
TRDY# are asserted.
I/O
High
C/BE3-0
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
In
Low
Bus Command/Byte Enables. During the address
In
Low
phase of a bus transaction, these pins define the
In
Low
bus command (see list above). During the data
in
Low
phase, these pins are byte enables that
determine which byte lanes carry meaningful
data: byte 0 corresponds to AD07, byte 1 to 8-15,
byte 2 to 16-23. and byte 3 to 2431
In
High
Initialization Device Select. Used as a chip select
during configuration read and write transactions
Description
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0100
-reserved-
0101
-reserved-
0110
Memory Read
0111
Memory Write
1000
-reserved
1001
-reserved-
1010
Configuration Read
1011
Configuration Write
1100
Memory read Multiple
1101
Dual Address Cycle
1110
Memory Read Line
1111
Memory Read & Invalidate
Support
Y
Y
Y
Y
Y
Y
Service Guide
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