Acer 390 Series Service Manual page 115

Table 2-8 65555 Pin Functions
Ball Pin Name
Display Memory Interface
D18 AA0 (CFG0)
Cl9 AAI (CFG1)
B20 AA2 (CFG2)
C18 AA3 (CFG3)
A20 AA4 (CFG4)
Bl9 AA5 (CFG5)
Al9 AA6 (CFG6)
B18 AA7 (CFG7)
C17 AA8 (CFG8)
D16 AA9 (CFG9)
D10 MA0 (TM0)
A10 MA1 (TM1)
B10 MA2 (CFG10)
C10 MA3 (CFG11)
A9 MA4 (CFG12)
B9 MA5 (CFG13)
A8 MA6 (CFG14)
C9 MA7 (CFG15)
B8 MA8 (RMD0)
A7 MA9 (RMDI)
C8 MA10 (RMD2)
B7 MA11 (RMD3)
A6 MA12 (RMD4)
C7 MA13 (RMD5)
B6 MA14 (RMD6)
A5 MA15 (RMD7)
D15 MB0 (RMA0)
B16 MBI (RMAI)
A17 MB2 (RMA2)
C15 MB3 (RMA3)
A16 MB4 (RMA4)
B15 MB5 (RMA5)
C14 MB6 (RMA6)
A15 MB7 (RMA7)
B14 MB8 (RMA8)
C13 MB9 (RMA9)
A14 MB10 (RMA10)
B13 MB11 (RMA11)
D12 MB12 (RMA12)
C12 MB13 (RMA13)
A13 MB14 (RMA14)
B12 MB15 (RMA15)
Major Chips Description
Type Active
I/O Both DRAM address bus for Bank 0 and Bank
l/O Both
l/O Both AA0 through AA9 also serve as configuration bits
l/O Both CFG0 through CFG9. Please see the
l/O Both descriptions for registers XR70 and XR71 for
/0 Both complete details on configuration
I
Both
l/O
Both
l/O
Both
l/O
Both
I/O
I/O High DRAM data bits 0-15.
l/O High
l/O High MA0 is also a test mode signal (Tri-Stale
I/O High Enable).
l/O High
l/O High MA1 is also a test mode signal (ICT Enable).
l/O High
I/O High MA2 through MA7 also serve as configuration
l/O High bits CFG10 through CFG15. Please see the
l/O High description for register XR71 for complete details
I/O High on configuration options.
l/O High
l/O High MA8 through MA15 are also serve as the data
I/O High bus for the BIOS ROM during system startup
l/O High (i.e., before the system enables the graphics
l/O High controller memory interface).
I/0 High DRAM data bits 16-31.
l/O High
l/O High MB0 through MB15, along with MDI I and MD12,
l/O High also serve as the address bus for the BIOS ROM
l/O High during startup (i.e., before he system enables the
l/O High graphics controller memory interface).
l/O High
l/O High Normally, a separate graphics BIOS ROM is not
l/O High required in portable computer designs, because
I/0 High the graphics BIOS is normally placed in the
l/O High same ROM devices as the system BIOS.
l/O High However, this graphics controller provides this
l/O High BIOS ROM interface capability for use in
l/O High development systems and add-in cards for flat
l/O High panel displays. Since the PCI bus specification
l/O High requires only one load on the PCI bus for each
PCI device, this BIOS ROM interface is provided
to allow access to the BIOS ROM through the
graphics controller chip, itself.
Description
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