Pci1250 Terminal Functions - Acer 390 Series Service Manual

Table 2-2

PCI1250 Terminal Functions

Name
PCI Address and Data Terminals
AD31 K18
AD30 K19
AD29 L20
AD28 L18
AD27 L19
AD26 M20
AD25 M19
AD24 M18
AD23 N19
AD22 N18
AD21 P20
AD20 P19
AD19 R20
AD18 R19
AD17 P17
AD16 R18
AD15 V18
AD14 Y19
AD13 W18
AD12 V17
AD11 U16
AD10 Y18
AD9 W17
AD8 V16
AD7 W16
AD6 U14
AD5 Y16
AD4 W15
AD3 V14
AD2 Y15
AD1 W14
AD0 Y14
C/BE3 M17
C/BE2 T20
C/BE1 W19
C/BE0 Y17
PAR Y20
2-6
No. I/O Type
I/O
I/O
Function
PCI address data bus. These signals make up the
multiplexed PCI address and data bus on the
primary interface. During the address phase of a
primary bus PCI cycle, AD31:0 contain a 32-bit
address or other destination. During the data
phase AD31 0 contain data.
PCI bus commands and byte enables. These
signals are multiplexed on the same PCI terminals.
During address phase of a primary bus PCI cycle,
C/BE3:0 define the bus command. During the data
phase, this four-bit bus is used as byte enables.
The byte enables determine which byte paths of the
full 32-bit data bus carry meaningful data. C/BE0
applies to byte 0 (AD7:0), C/BE1 applies to byte 1
(AD15:8), C/be2 applies to byte 2 (AD23:16) and
C/BE3 applies to byte 3 (AD31:24).
PCI bus party In all PCI bus read and write cycles
the PCI1250A calculates even parity across the
AD31:0 and C/BE3:0 buses. As an initiator during
PCI cycles, the PCI1250A outputs this parity
indicator with a one PCLK delay. As a target during
PCI cycles. the calculated parity is compared to the
initiators parity indicator. A miscompare can result
in the assertion of a parity error (PERR).
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