Acer 390 Series Service Manual page 117

Table 2-8 65555 Pin Functions
Ball Pin Name
Flat Panel Display Interface
W6 P0
V7 P1
Y6 P2
W7 P3
V8 P4
Y7 P5
W8 P6
U9 P7
V9 P8
Y8 P9
W9 P10
Y9 P11
V10 P12
W10 P13
Y10 P14
U10 P15
U11 P16
Y11 P17
W11 P18
V11 P19
Y12 P20
Y13 P21
V12 P22
U12 P23
W13 P24
Y14 P25
V13 P26
W14 P27
Y15 P28
V14 P29
W15 P30
Y16 P31
V15 P32
Y17 P33
W16 P34
U15 P35
Y5 SHFCLK
W5 FLM
Y4 LP
(CL1)(DE)(BLANK#)
V6 M
(DE)(BLANK#)
V5 ENAVDD
W4 ENAVEE(ENABKL)
U6 ENABKL
Major Chips Description
Type Active
Out High Flat panel data bus of up to 36-bits
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High
Out High Shift Clock. Pixel clock for nat panel data
Out High First Line Marker. Flat Panel equivalent of
VSYNC
Out High Latch Pulse (may also be called CL1 ). Flat
Panel equivalent of HSYNC. May also be
configured as DE (display enable) or BLANK#
output
Out High M signal for panel AC drive control (may also be
called ACDCLK). May also be configured as DE
(display enable) or BLANK# output
I/O high Power sequencing control for panel driver
electronics voltage VDD
I/O High Power sequencing control for panel bias voltage
VEE. May also be configured as ENABKL
I/O High Power sequencing control for enabling the
backlight
Description
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