Acer 390 Series Service Manual page 121

Table 2-8 65555 Pin Functions (continued)
Ball Pin Name
P4,
U14,
U7,
J9-12
K9-12
L9-12
M9-12
Y1 RGND
H4,N4 BVCC
U8 DVCC
D13 MVCC
H17
N17
U13 VVCC
Video Interface
V16 VREF
W17 HREF
Y18 VCLK
V17 PCLK(VCLKOUT)
R18 VP0
U20 VP1
T19 VP2
R17 VP3
T18 VP4
U19 VP5
V20 VP6
T17 VP7
U18 VP8
V19 VP9
W20 VP10
W19 VP11
U17 VP12
V18 VP13
Y19 VP14
V18 VP15
Note: All signals listed above are powered by VVCC and GND.
Boundary Scan
A1 TMS
B2 TCLK(DCLKIN)
Major Chips Description
Type Active
GND Internal reference GND, should be tied to GND
VCC - Power (Bus Interface), 3.3V
VCC - Power (Flat Panel Interface), 3.3V
VCC - Power (Memory Interface), 3.3V.
VCC - Power (Video Interface), 3.3V.
I/O High Vertical reference input for video data port.
In High Horizontal reference input for video data port
In High Clock input for video data port.
Out High Outputs DCLK, or DCLK divided by 2. See the
description for register XR60 for complete details.
Usable with either the video data port or the flat
panel interface. May also be configured to output
VCLK in test mode.
In High Data bus for video data port.
In High
In High
When used as a ZV-Port interface, VP0-7
In High
correspond to Y0-7, and VP8-15 correspond to
In High
UV0-7.
In High
In High
In High
In High
In High
In High
In High
In High
In High
In High
In High
In High Test mode select for boundary scan
In High Test clock for boundary scan. Can be configured to
be used as an input for an externally provided
DCLK through a strapping option. See the
descriptions for registers XR70 and XRCF for
complete details
Description
2-75