Analog Devices SHARC Series Getting Started Manual page 23

execution (including single cycle multiply accumulates [MACs]), SHARC
processors are designed for maximum I/O and memory access bandwidth.
This balance of core speed, memory integration, and I/O bandwidth
achieves the sustained performance critical to real-time applications.
Table 1-1. ADSP-2126x SHARC Processor Specifications
Frequency (MHz)
On-Chip RAM
On-Chip ROM
SRC
PWM
UART
SPI
SPDIF
TWI
Timer
SPORT
SRU
DTCP
PCG
Temp. Grade
Execution from Ext. Memory?
Getting Started With SHARC Processors
Introduction to SHARC Processors
ADSP-21261 ADSP-21262
150 200
1M bit 2M bit
3M bit 4M bit
0 0
0 0
0 0
1 1
0 0
0 0
3 3
4 6
1 1
0 0
2 2
–40°C to +85°C –40°C to +85°C
No No
ADSP-21266
200
2M bit
4M bit
0
0
0
1
0
0
3
6
1
0
2
–40°C to +105°C
No
1-9