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Table 1-13
GPIO Port Definition Map II
GPIO
P2.1
P2.2 (SM5_BAYSW)
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0 (SM5_RXD)
P3.1 (SM5_TXD)
P3.2 (SM5_DOCKSW)
P3.3 (CF5_DOCKED)
P3.4 (SM5_LIDSW)
P3.5 (SM5_OVTMP#)
P3.6
P3.7 (SM5_ON_RES_SW)
P4.0 (SM5_FANON)
P4.1
P4.2 (SM5_FLOATREQ#)
P4.3 (SM5_UNDOCK_GNT#)
P4.4 (SM5_ICONT)
P4.5 (SM5_FLAOTGNT#)
P4.6 (SM5_PWRRDYB)
P4.7 (SM5_SYSRDY)
P5.0 (CHARGSP)
P5.1 (SM5_VBAT_MAIN)
P5.2 (SM5_ACPWRGD)
P5.3 (SM5_NBPWRGD)
P5.4 (SM5_ATFINT)
P5.5 (SM5_THERM_SYS)
P5.6 (SM5_ACIN_AUX)
P5.7 (SM5_ACIN_MAIN)
PWM1# (SM5_CONT)
PWM0# (SM5_BRIT)
1.6.6
PCI Devices Assignment
Table 1-14
PCI Devices Assignment
System Introduction
I/O
Description
O
NC
I
Detect FDD/CD bay installed or not
O
NC
O
NC
O
NC
O
NC
O
NC
I
Receiving data from KBC to SMC
O
Transmitting data from SMC to KBC
I
Dock switch sense
I
Detect completely docked or not
I
Lid switch sense
O
CPU or system over temperature
O
NC
O
ON/RESUME switch for Japan version
O
Fan control
NC
O
Docking float request
O
Undock grant
I
Charge current control
I
Docking float grant
O
Power ready, delay about 4ms after power good
O
NC
I
Charging set point
I
Main battery detection
I
AC source power good
I
3V, 5V, processor module power good
I
CPU thermal interrupt (panic)
I
System thermal input (analog)
I
Aux AC adapter in
I
Main AC adapter in
O
LCD contrast
O
LCD brightness
1-23
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