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Acer TM7100 Series Service Manual

Acer TM7100 Series Service Manual

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TM7100 Series
Notebook Computer
Service Guide
PART NO.: 49.42A01.001
DOC. NO.: SG238-9712A
PRINTED IN TAIWAN

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Summary of Contents for Acer TM7100 Series

  • Page 1 TM7100 Series Notebook Computer Service Guide PART NO.: 49.42A01.001 DOC. NO.: SG238-9712A PRINTED IN TAIWAN...
  • Page 2 Further, Acer Incorporated reserves the right to revise this publication and to make changes from time to time in the contents hereof without obligation of Acer Incorporated to notify any person of such revision or changes.

  • Page 3: System Introduction

    About this Manual Purpose This service guide aims to furnish technical information to the service engineers and advanced users when upgrading, configuring, or repairing the TM7100 series notebook computer. Manual Structure This service guide contains technical information about the TM7100 series notebook computer. It consists of three chapters and five appendices.
  • Page 4 Appendix D Schematics This appendix contains the schematic diagrams for the system board. Appendix E BIOS POST Checkpoints This appendix lists and describes the BIOS POST checkpoints. Conventions The following are the conventions used in this manual: Represents text input by the user. Text entered by user Denotes actual messages that appear onscreen.

  • Page 5: Table Of Contents

    Table of Contents Chapter 1 System Introduction Features ......................1-1 1.1.2 FlashStart Automatic Power-On ............1-2 Ports ........................1-3 1.2.1 Rear Panel Ports................... 1-3 1.2.2 Left Panel Ports ..................1-4 1.2.3 Indicator Lights..................1-5 1.2.4 Hot Keys ....................1-6 1.2.5 Automatic Tilt..................
  • Page 6 1.6.14 PCMCIA....................1-35 1.6.15 Parallel Port ..................1-36 1.6.16 Serial Port....................1-36 1.6.17 Touchpad.....................1-36 1.6.18 SIR/FIR....................1-37 1.6.19 LCD .....................1-37 1.6.20 CD-ROM....................1-38 1.6.21 Diskette Drive ..................1-38 1.6.22 Hard Disk Drive..................1-39 1.6.23 Keyboard .....................1-39 1.6.24 Battery ....................1-40 1.6.25 DC-DC Converter.................1-40 1.6.26 DC-AC Inverter ..................1-41 1.6.27 AC Adapter ..................1-41 System Block Diagrams..................1-42 1.7.1...
  • Page 7 2.4.3 Pin Diagram ..................2-40 2.4.4 Pin Descriptions ...................2-41 Philips 87C552 System Management Controller ..........2-43 2.5.1 Features....................2-43 2.5.2 Block Diagram ..................2-44 2.5.3 Pin Diagram ..................2-45 2.5.4 Pin Descriptions ...................2-46 NS87338VJG Super I/O Controller..............2-48 2.6.1 Features....................2-48 2.6.2 Block Diagram ..................2-50 2.6.3 Pin Diagram ..................2-51 2.6.4 Pin Description..................2-52 CL-PD6832: PCI-to-CardBus Host Adapter ............2-59...
  • Page 8 Advanced System Configuration................3-5 3.3.1 Internal Cache..................3-5 3.3.2 External Cache ..................3-5 3.3.3 Enhanced IDE Features .................3-5 3.3.4 Onboard Communication Ports ..............3-6 3.3.5 Onboard USB..................3-6 3.3.6 Reset PnP Resources ................3-7 Power Saving Options ..................3-8 3.4.1 When Lid is Closed ................3-8 3.4.2 Suspend to Disk on Critical Battery ............3-8 3.4.3 Display Always On .................3-8 3.4.4...
  • Page 9 4.8.1 Detaching the Lower Housing from the Inside Assembly ......4-14 4.8.2 Detaching the Upper Housing from the Inside Assembly ......4-15 4.8.3 Removing the Touchpad ..............4-16 4.8.4 Removing the Main Board..............4-16 Disassembling the Display ..................4-19 Appendices Appendix A Model Number Definition Appendix B Exploded View Diagram Appendix C...
  • Page 10 List of Figures Lid Switch ......................1-2 Rear Port Location....................1-3 Left Port Location ....................1-4 Indicator Lights .....................1-5 System Board (Top Side)..................1-12 System Board (Bottom Side)................1-13 Media Board (Top Side)..................1-14 Media Board (Bottom Side).................1-15 Mainboard Jumpers and Connectors (Top Side) ..........1-16 1-10 Mainboard Jumpers and Connectors (Bottom Side) ..........1-17 1-11 Media Board Jumpers and Connectors (Top Side) ..........1-18...
  • Page 11 Installing and Removing Memory................. 4-8 Removing the Display Hinge Covers..............4-10 4-10 Removing the Center Hinge Cover ..............4-10 4-11 Lifting Out the Keyboard ..................4-11 4-12 Unplugging the Keyboard Connectors and Removing the Keyboard....4-11 4-13 Removing the CPU Heat Sink................4-12 4-14 Removing the CPU Module.................4-12 4-15 Unplugging the Display Cable ................4-13 4-16...
  • Page 12 List of Tables Rear Port Descriptions ..................1-3 Left Port Descriptions....................1-5 Indicator Light Descriptions...................1-5 Hot Key Descriptions ....................1-6 Eject Menu Item Descriptions ................1-7 System Specifications...................1-9 Mainboard Jumpers Pads Settings (Bottom Side) ..........1-17 System Memory Map..................1-19 Interrupt Channel Map ..................1-19 1-10 I/O Address Map....................1-19 1-11 DMA Channel Map....................1-20 1-12...
  • Page 13 1-35 Battery Specifications ..................1-40 1-36 DC-DC Converter Specifications.................1-40 1-37 DC-AC Inverter Specifications ................1-41 1-38 AC Adapter Specifications ..................1-41 1-39 Environmental Requirements................1-44 1-40 Mechanical Specifications...................1-45 Major Chips List ....................2-1 82371AB Pin Descriptions..................2-9 NM2160 Pin Descriptions..................2-31 NMA1 Pin Descriptions ..................2-41 87C552 Pin Descriptions..................2-46 NS87338VJG Pin Descriptions................2-52 CL-PD6832 Pin Descriptions................2-62...

  • Page 14: Chapter 1 System Introduction

    C h a p t e r C h a p t e r System Introduction The computer is packed with features that make it as easy to work with as it is to look at. Here are some of the computer’s features: Features PERFORMANCE ®...

  • Page 15: Flashstart Automatic Power-On

    Ergonomically-positioned touchpad pointing device EXPANDABILITY CardBus PC Card (PCMCIA) slots (two type II/I or one type III) with Zoomed Video port function Mini-dock option with two CardBus PC Card slots (two type II/I or one type III) USB port onboard Upgradeable memory and hard disk 1.1.2 FlashStart Automatic Power-On...

  • Page 16: Ports

    Ports The computer’s ports allow you to connect peripheral devices to your computer just as you would to a desktop PC. The main ports are found on the computer’s rear panel. The computer’s left panel contains the computer’s multimedia ports and PC card slots. 1.2.1 Rear Panel Ports The computer’s rear panel contains the computer’s main ports and connectors as shown in the...

  • Page 17: Left Panel Ports

    UNIVERSAL SERIAL BUS (USB) PORT The computer’s USB (Universal Serial Bus) port located on the rear panel allows you to connect peripherals without occupying too many resources. Common USB devices include the mouse and keyboard. FAST INFRARED (FIR) PORT The computer’s FIR (fast infrared) port located on the rear panel allows you to transfer data to IR- aware machines without cables.

  • Page 18: Indicator Lights

    Table 1-2 Left Port Descriptions Port Icon Connects to... PC Card slots Two type I/II PC Cards or one type III Card Microphone-in/ Line-in External microphone or line input device Speaker-out/ Line-out Amplified speakers or headphones PC CARD SLOTS The computer contains two PC card slots on the left panel that accommodate two type I/II or one type III PC card(s).

  • Page 19: Hot Keys

    1.2.4 Hot Keys The computer’s special Fn key, used in combination with other keys, provides “hot-key” combinations that access system control functions, such as screen contrast, brightness, volume output, and the BIOS setup utility. Table 1-4 Hot Key Descriptions Hot Key Icon Function Description...

  • Page 20: Eject Menu Item Descriptions

    Table 1-4 Hot Key Descriptions Hot Key Icon Function Description Brightness Up Increases screen brightness Fn+ÿ+ Brightness Down Decreases screen brightness Fn+ÿ+ Contrast Up Increases screen contrast (not available for TFT displays) Fn+ÿ+ Contrast Down Decreases screen contrast (not available for TFT displays) Fn+ÿ+ Fuel Gauge Up With the fuel gauge displayed, moves the fuel gauge up...

  • Page 21: Automatic Tilt

    1.2.5 Automatic Tilt The computer (models with 12.1-inch LCDs) can automatically tilt the keyboard to a six-degree angle whenever you open the lid to provide a comfortable typing angle similar to desktop keyboards. To set the automatic tilt feature, follow these steps: 1.

  • Page 22: System Specification Overview

    System Specification Overview Table 1-6 System Specifications Item Standard Optional ® Microprocessor Intel Pentium processor with MMX™ technology Memory System / Main 32MB Expandable to 128MB using Dual 64-bit memory banks 8/16/32/64MB soDIMMs External cache 512KB L2 cache (synchronous SRAM) Flash BIOS 256KB Storage system...
  • Page 23 Table 1-6 System Specifications Item Standard Optional I/O Ports One type III or two type II PC Card slot(s) LAN card or other PC cards (continued) One fast infrared port (IrDA-compliant) External IR adapter One 3.5mm minijack microphone-in/line-in Microphone or line-in device jack One 3.5mm minijack speaker-out/line-out Speakers or headphones...

  • Page 24: Board Layout

    Board Layout...

  • Page 25: System Board (Top Side)

    1.4.1 System Board (Top Side) Figure 1-5 System Board (Top Side)

  • Page 26: System Board (Bottom Side)

    1.4.2 System Board (Bottom Side) Figure 1-6 System Board (Bottom Side)

  • Page 27: Media Board (Top Side)

    1.4.3 Media Board (Top Side) Figure 1-7 Media Board (Top Side)

  • Page 28: Media Board (Bottom Side)

    1.4.4 Media Board (Bottom Side) Figure 1-8 Media Board (Bottom Side)

  • Page 29: Jumpers And Connectors

    Jumpers and Connectors 1.5.1 Mainboard CN10 CN11 CN12 CN13 CN14, CN15 CN8, CN9 Multimedia board connector VGA port CN10 FDD/CD-ROM connector Mini dock port CN14, CN15 CPU board connector Parallel port CN13 Hard disk drive connector Serial Port CN12 Speaker-out/Line-out Jack PS2 mouse/keyboard port CN11 Microphone-in/Line-in Jack...

  • Page 30: Mainboard Jumpers And Connectors (Bottom Side)

    Mainboard Jumpers Pads Settings (Bottom Side) Jumper Pad Descriptions Settings SW2(1) Keyboard type selection OFF: Other keyboard ON: Japan keyboard SW2(2) Password settings OFF: Enable password ON: Bypass password SW2(3) BIOS type selection OFF: Acer BIOS ON: OEM BIOS SW2(4) Reserved...

  • Page 31: Media Board

    1.5.2 Media Board CN4 CN5 CN6 Lid switch Touchpad connector LCD connector CN4, CN5 Keyboard connector Figure 1-11 Media Board Jumpers and Connectors (Top Side) CN7, CN8 Mainboard connector PCMCIA socket connector Figure 1-12 Media Board Jumpers and Connectors (Bottom Side)

  • Page 32: System Configurations And Specifications

    System Configurations and Specifications 1.6.1 System Memory Map Table 1-8 System Memory Map Address Range Definition Function 000000 -09FFFF 640 KB memory Base memory 0A0000 -0BFFFF 128 KB video RAM Reserved for graphics display buffer 0C0000 -0CBFFF Video BIOS Video BIOS 0CC000 -0CDFFF System CardBus 0CE000 -0CFFFF...

  • Page 33: Dma Channel Map

    Table 1-10 I/O Address Map Address Range Device 060 -06E Keyboard controller chip select 070 -071 Real-time clock and NMI mask 080 -08F DMA page register 0A0 -0A1 Interrupt controller-2 0C0 -0DF DMA controller-2 1F0 -1F7 Hard disk select 3F6 -3F7 Hard disk select 170 -177 CD-ROM select...

  • Page 34: Gpio Port Definition Map

    1.6.5 GPIO Port Definition Map Table 1-12 GPIO Port Definition Map I GPIO/Signal Pin # Description GPIO Pin Assignment: PIIX4 SUSA# (PX3_SUSA#) 0: Power down clock generator GPO0 (PX3_DOCKRST#) 0 : Enable docking reset GPO1 (PX3_HDPON) 1: Turn on HDD power GPO2 (PX3_ CD/FDPON) 1: Turn on CD/FDD power GPO3 (PX3_ HDRST#)
  • Page 35 Table 1-12 GPIO Port Definition Map I GPIO/Signal Pin # Description GPI1 (DK3_DOCKIRQ#) 0: Detect Docking IRQ GPI2/REQA# (PX3_OEM0) OEM detection GPI3/REQB# (SM5_BAYSW) Detect FDD/CD bay 1: installed, 0: not installed GPI4/REQC# (CF5_FDD/CD#) Detect FDD or CD installed 1: FDD, 0: CD GPI5/APICREQ# GPI6/IRQ8# (RT3_IRQ8#) 0: RTC wake...

  • Page 36: Gpio Port Definition Map Ii

    Table 1-13 GPIO Port Definition Map II GPIO Description P1.7 (IS5_IRQ12) IRQ12 P2.0 (KB5_MEMB0A0) Address 0 of memory bank 0 P2.1 (KB5_MEMB0A1) Address 1 of memory bank 0 P2.2 (KB5_MODE) Detect KBD mode (1:US/EC 0:Japan) P2.3 P2.4 (KB5_MEMB1A0) Address 0 of memory bank 1 P2.5 (KB5_PSWD) Enable Password P2.6 (KB5_MEMB1A1)

  • Page 37: Pci Devices Assignment

    Table 1-13 GPIO Port Definition Map II GPIO Description P2.0 P2.1 P2.2 (SM5_BAYSW) Detect FDD/CD bay installed or not P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 (SM5_RXD) Receiving data from KBC to SMC P3.1 (SM5_TXD) Transmitting data from SMC to KBC P3.2 (SM5_DOCKSW) Dock switch sense P3.3 (CF5_DOCKED)

  • Page 38: Power Management

    Since the power management is implemented by linking with APM interface closely, the APM function in Win95 or Win3.1 must be enabled and set to advanced level for optimum power management and the driver that installed in system must be Acer authorized and approved.

  • Page 39: Pmu Timers List

    1.6.7.1 PMU Timers There are several devices related timers available on the V1-LS chip. Each timer may have zero or more devices assigned to the timer for the purpose of retriggering the timer. Table 1-15 PMU Timers List Item Descriptions Video timer Timer value 30sec, 1min, 1.5min, 2min, 2.5min, 3min, 3.5min, 4min, 4.5min, 5min, 6min, 7min,...
  • Page 40 Table 1-15 PMU Timers List Item Descriptions System activities System activities and timer Power off either or both FDD and CD-ROM. Tri-state FDD and CD-ROM retriggers interfaces and stop IDE controller clock. Timer retriggers The I/O access to 3F2, 3F4, 3F5(FDD), 3F7, 376(CD ROM) will retrigger the timer.
  • Page 41 3. CD-ROM Reset [pin-U13 of U21(PX3_CDRST#) of PIIX4]. The reset pin is used to assert the hard reset needed for the CD-ROM during power up. The reset pin is asserted before CD-ROM power up and is deasserted after CD-ROM power up and before the buffer is enabled.
  • Page 42 Recovery from power down is the opposite procedure. SIR (UART) The FIR port is basically UART2. The UART operates off of a 14MHz clock. The IR port has a DA converter. The UART2 disable control circuit is within the 87338 chip. 1.
  • Page 43 The CPU clock. The clock to the CPU can be physically stopped. The chip is static, so the current state is retained. During a clock stop state, the CPU is stopped and the internal cache and external bus signals are inoperative. Therefore, any bus master or DMA activity is halted as well.

  • Page 44: Cpu Module

    For suspend-to-disk, all devices are read, saved to local memory and the local memory, video memory are saved to a disk file which is created by SLEEP MANAGER utility. The machine is then commanded to an off state. Resume events for zero-volt suspend(suspend-to-disk) The only resume event for zero-volt suspend is the raising of the lid of the computer.

  • Page 45: Bios

    1.6.9 BIOS Table 1-17 BIOS Specifications Item Specification BIOS programming vendor Acer BIOS version V3.0 BIOS ROM type Intel 28F002, Flash ROM with boot block protection BIOS ROM size 256KB BIOS ROM package type 40-pin TSOP Same BIOS for TFT LCD type...

  • Page 46: Video Memory

    1.6.10.1 SIMM Memory Combination List Table 1-19 SIMM Memory Combination List RAM Size Bank A Bank B 16MB 16MB 16MB 16MB 16MB 24MB 16MB 24MB 16MB 32MB 16MB 16MB 32MB 32MB 32MB 32MB 40MB 32MB 40MB 32MB 48MB 16MB 32MB 48MB 32MB 16MB...

  • Page 47: Video Display Modes

    1.6.12 Video Display Modes Table 1-21 Video Display Specification Item Specification Chip vendor NeoMagic Chip name NMG2160 Chip voltage 3.3 Volts ZV port support (Y/N) Graph interface (ISA/VESA/PCI) PCI bus Max. resolution (LCD) 800x600 (16M colors) True Color Max. resolution (Ext. CRT) 1024x768 (64K colors) High Color 1.6.12.1 External CRT Resolution Modes...

  • Page 48: Audio

    1.6.13 Audio Table 1-24 Audio Specifications Item Specification Chipset Neomagic-3097 Audio onboard or optional Built-in Mono or stereo stereo Resolution 16-bit Compatibility Sound Blaster Game, Windows Sound System, Plug&Play ISA 1.0a Music synthesizer 20-voice, 72 operator, FM music synthesizer Mixed sound sources Voice, Synthesizer, Line-in, Microphone, CD Voice channel 8-/16-bit, mono/stereo...

  • Page 49: Parallel Port

    1.6.15 Parallel Port Table 1-26 Parallel Port Specifications Item Specification Number of parallel ports ECP/EPP support Yes (by BIOS Setup) ECP DMA channel (by BIOS Setup) DRQ1 or DRQ3 Connector type 25-pin D-type Connector location Rear side Selectable parallel port (by BIOS Setup) Parallel 1 (378h, IRQ7) or Parallel 2 (3BCh, IRQ7) or Parallel 3 (278h, IRQ5) or...

  • Page 50: Sir/Fir

    1.6.18 SIR/FIR Table 1-29 SIR/FIR Specifications Item Specification Vendor & model name IBM(31T1100A) Input power supply voltage Transfer data rate 115.2 Kbit/s(Max)(SIR)~4 Mbit/s(FIR)(Max) Transfer distance 100cm Compatible standard IrDA (Infrared Data Association) Output data signal voltage level Active Non-active Vcc-0.5 Angle of operation Number of IrDA ports 16550 UART support...

  • Page 51: Cd-Rom

    1.6.20 CD-ROM Table 1-31 CD-ROM Specifications Item Specification Vendor & model name KYUSHU MATSHITA: UJDA110 Internal CD-ROM/FDD hot-swappable BIOS auto-detect CD-ROM existence BIOS support boot from CD drive feature Performance specification Speed 2100KB/sec(14X speed) Access time 150ms Buffer memory 128kbyte Interface Enhanced IDE (ATAPI) compatible (communicate with system via system E-IDE channel 2)

  • Page 52: Hard Disk Drive

    1.6.22 Hard Disk Drive Table 1-33 Hard Disk Drive Specifications Item Specification Vendor & Model Name IBM DTCA-23240 IBM DTCA-24090 Drive Format Capacity (GB) 4.09 3.24 Bytes per sector Logical heads Logical sectors Logical cylinders 6304 7944 Physical read/write heads Disks Rotational speed (RPM) 4000...

  • Page 53: Battery

    1.6.24 Battery Table 1-35 Battery Specifications Item Specification Vendor & Model Name Sony BTP-S31 Battery Gauge Battery type Li-Ion Cell capacity 2700mAH Cell voltage 3.6V Number of battery cell 6-Cell Package configuration 3 serial, 2 parallel Package voltage 10.8V Package capacity 58.3WH Second battery 1.6.25...

  • Page 54: Dc-Ac Inverter

    1.6.26 DC-AC Inverter DC-AC inverter is used to generate very high AC voltage, then supply to LCD CCFT backlight use. The DC-AC inverter area should be void to touch while the system unit is turned on. Table 1-37 DC-AC Inverter Specifications Item Specification Vendor &...

  • Page 55: System Block Diagrams

    System Block Diagrams 1.7.1 System Functional Block Diagram Figure 1-13 System Functional Block Diagram...

  • Page 56: System Bus Block Diagram

    1.7.2 System Bus Block Diagram Figure 1-14 System Bus Block Diagram...

  • Page 57: Environmental Requirements

    Environmental Requirements Table 1-39 Environmental Requirements Item Specification Temperature Operating (ºC) +5 ~ +35 Non-operating(ºC)(unpacked) -10 ~ +60 Non-operating(ºC)(storage package) -20 ~ +60 Humidity Operating (non-condensing) 20% ~ 80% Non-operating (non-condensing) 20% ~ 80% (unpacked) Non-operating (non-condensing) (storage 20% ~ 90% package) Operating Vibration (sine mode) Operating...

  • Page 58: Mechanical Specifications

    Mechanical Specifications Table 1-40 Mechanical Specifications Item Specification Weight (includes battery and FDD) 12.1 TFT SVGA LCD and 12.5mm HDD 3.3 kgs (7.2 lbs) Adapter 230 g (0.52 lb) Dimensions round contour 297~313mm x 233~240mm x 50~53mm main footprint 11.7” x 9.1” x 2”...

  • Page 59: Chapter 2 Major Chips Description

    C h a p t e r C h a p t e r Major Chips Description This chapter discusses the major components. Major Component List Table 2-1 Major Chips List Component Vendor Description PIIX4 Intel NM2160 NeoMagic Flat Panel Video Accelerator NMA1 NeoMagic Audio chip...

  • Page 60: Intel Piix4

    Intel PIIX4 PIIX4 is a multi-function PCI device that integrates many system-level functions. PCI to ISA/EIO Bridge PIIX4 is compatible with the PCI Rev 2.1 specification, as well as the IEEE 996 specification for the ISA (AT) bus. On PCI, PIIX4 operates as a master for various internal modules, such as the USB controller, DMA controller, IDE bus master controller, distributed DMA masters, and on behalf of ISA masters.
  • Page 61 The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, refresh request, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for these three counters.

  • Page 62: Features

    Enhanced Power Management PIIX4’s power management functions include enhanced clock control, local and global monitoring support for 14 individual devices, and various low-power (suspend) states, such as Power-On Suspend, Suspend-to-DRAM, and Suspend-to-Disk. A hardware-based thermal management circuit permits software-independent entrance to low-power states. PIIX4 has dedicated pins to monitor various external events (e.g., interfaces to a notebook lid, suspend/resume button, battery low indicators, etc.).
  • Page 63 Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0 Specification and OS Directed Power Management Integrated IDE Controller Independent Timing of up to 4 Drives PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec Supports “Ultra DMA/33” Synchronous DMA Mode Transfers up to 33 Mbytes/sec Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers Supports Glue-less “Swap-Bay”...

  • Page 64: Architecture Block Diagram

    The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI- to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock.

  • Page 65: Block Diagram

    2.2.3 Block Diagram Figure 2-2 PIIX4 Simplified Block Diagram...

  • Page 66: Pin Descriptions

    2.2.4 Pin Descriptions This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level.

  • Page 67: 82371Ab Pin Descriptions

    Table 2-2 82371AB Pin Descriptions Name Type Description PCI BUS INTERFACE AD[31:0] PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction consists of an address phase followed by one or more data phases.
  • Page 68 Table 2-2 82371AB Pin Descriptions Name Type Description IRDY# INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted.
  • Page 69 Table 2-2 82371AB Pin Descriptions Name Type Description TRDY# TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that PIIX4, as a Target, has place valid data on AD[31:0].
  • Page 70 Table 2-2 82371AB Pin Descriptions Name Type Description IOW# I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns the ISA Bus. IOW# is an input when an external ISA master owns the ISA Bus.
  • Page 71 Table 2-2 82371AB Pin Descriptions Name Type Description SA[19:0] SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection with the granularity of 1 byte within the 1-Megabyte section of memory defined by the LA[23:17] address lines. The address lines SA[19:17] that are coincident with LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.
  • Page 72 Table 2-2 82371AB Pin Descriptions Name Type Description KBCCS#/ KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O read or write accesses to KBC locations 60h and 64h. It is driven combinatorially GPO26 from the ISA addresses SA[19:0] and LA[23:17]. If the keyboard controller does not require a separate chip select, this signal can be programmed to a general purpose output.
  • Page 73 Table 2-2 82371AB Pin Descriptions Name Type Description XOE#/ X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output enable of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data GPO23 bus, SD[7:0]. XOE# is asserted anytime a PIIX4 supported X-Bus device is decoded, and the devices decode is enabled in the X-Bus Chip Select Enable Register (BIOSCS#, KBCCS#, RTCCS#, MCCS#) or the Device Resource B (PCCS0#) and Device Resource C (PCCS1#).
  • Page 74 Table 2-2 82371AB Pin Descriptions Name Type Description INTERRUPT CONTROLLER/APIC SIGNALS APICACK#/ APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after its internal buffers are flushed in response to the APICREQ# signal. When the GPO12 I/O APIC samples this signal asserted it knows that PIIX4’s buffers are flushed and that it can proceed to send the APIC interrupt.
  • Page 75 Table 2-2 82371AB Pin Descriptions Name Type Description IRQ 12/M INTERRUPT REQUEST 12. In addition to providing the standard interrupt function as described in the pin description for IRQ[3:7,9:11,14:15], this pin can also be programmed to provide the mouse interrupt function. When the mouse interrupt function is selected, a low to high transition on this signal is latched by PIIX4 and an INTR is generated to the CPU as IRQ12.
  • Page 76 Table 2-2 82371AB Pin Descriptions Name Type Description INIT INITIALIZATION. INIT is asserted in response to any one of the following conditions. When the System Reset bit in the Reset Control Register is reset to 0 and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by asserting INIT.
  • Page 77 Table 2-2 82371AB Pin Descriptions Name Type Description PCICLK FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK provides timing for all transactions on the PCI Bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge.
  • Page 78 Table 2-2 82371AB Pin Descriptions Name Type Description PDDACK# PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA data transfer cycle.
  • Page 79 Table 2-2 82371AB Pin Descriptions Name Type Description PIORDY PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is directly driven by the corresponding IDE device IORDY signal. In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching data on rising and falling edges of STROBE.
  • Page 80 Table 2-2 82371AB Pin Descriptions Name Type Description SDDREQ SECONDARY DISK DMA REQUEST. This input signal is directly driven from the IDE device DMARQ signal. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function. It is not associated with any AT compatible DMA channel.
  • Page 81 Table 2-2 82371AB Pin Descriptions Name Type Description USBP0+, SERIAL BUS PORT 0. This signal pair comprises the differential data signal for USB port 0. USBP0– During Reset: High-Z After Reset: High-Z During POS: High-Z USBP1+, SERIAL BUS PORT 1. This signal pair comprises the differential data signal for USB port 1.
  • Page 82 Table 2-2 82371AB Pin Descriptions Name Type Description SMBALERT#/ SM BUS ALERT. Input used by System Management Bus logic to generate an interrupt (IRQ or SMI) or power management resume event when enabled. If this GPI11 function is not needed, this pin can be used as a general-purpose input. SMBCLK SM BUS CLOCK.
  • Page 83 Table 2-2 82371AB Pin Descriptions Name Type Description GENERAL PURPOSE INPUT AND OUTPUT SIGNALS Some of the General Purpose Input and Output signals are multiplexed with other PIIX4 signals. The usage is determined by the system configuration. The default pin usage is shown in Table 1 and Table 2. The configuration can be selected via the General Configuration register and X-Bus Chip Select register.
  • Page 84 Signal Multiplexed Default Control Register Notes Name With and Bit (PCI Function 1) GPO0 Non-multiplexed GPO which is always available. GPO[1:7] LA[17:23] GENCFG Available as GPO only if EIO mode. Bit 0 GPO8 Non-multiplexed GPO which is always available. The GPO[8] signal will be driven low upon removal of power from the PIIX4 core power plane.
  • Page 85 Table 2-2 82371AB Pin Descriptions (continued) Name Type Description CONFIG1 This input signal is used to select the type of CONFIGURATION SELECT 1. microprocessor being used in the system. If CONFIG1=0, the system contains a Pentium microprocessor. If CONFIG1=1, the system contains a Pentium II microprocessor.

  • Page 86: Features

    NM2160 The NM2160 is a high performance Flat Panel Video Accelerator that integrates in one single chip, 2 Mbytes of High Speed DRAM, 24-bit true-color RAMDAC, Graphics/Video Accelerator, Dual clock synthesizer, TV Out support, ZV(Zoomed Video) port, Z-Buffer Data Stripping, PCI Bus Mastering and a high speed glueless 32-bit PCI 2.1 compliance interface.
  • Page 87 High Speed 2Mbytes of integrated DRAM 128 bit Memory Interface Bus Support PCI 2.1 compliance Local Bus(Zero wait states) 3.3Volts or 5Volts operation EMI Reduction Spread Spectrum Clocking technology for reduced panel EMI Hardware Cursor and Icon Relocatable Hardware Cursor and Icon 64X64 Hardware Cursor 64X64 or 128X128 Hardware Icon Green PC Support...

  • Page 88: Pin Diagram

    2.3.2 Pin Diagram Figure 2-3 NM2160 Pin Diagram...

  • Page 89: Pin Descriptions

    2.3.3 Pin Descriptions Conventions used in the pin description types: Input into NM2160 Output from NM2160 Input and Output to/from NM2160 Tri-state during un-driven state S/T/S Before becoming tri-state the pin will be driven inactive Open-drain type output Table 2-3 NM2160 Pin Descriptions Pin name Number...
  • Page 90 Table 2-3 NM2160 Pin Descriptions Pin name Number Description FRAME# Frame This active-low signal is driven by the bus master to indicate the beginning and duration of an access. NM2160 drives this pin in the Bus Master mode Parity Even parity across AD31:0&C/BE3:0# is driven by the bus master during address and write data phases and driven by NM2160 during read data phases TRDY#...
  • Page 91 Table 2-3 NM2160 Pin Descriptions Pin name Number Description XCKEN External Clock Enable This pin is used to select between internally synthesized clocks or externally supplied clocks. A low level on the pin selects internal mode and a high level selects external mode.
  • Page 92 Table 2-3 NM2160 Pin Descriptions Pin name Number Description FPVEE Flat Panel VEE This is used to control the bias power to the panels FPBACK Flat Panel Backlight This is used to control the backlight power to the panels or as a General Purpose Output Pin as defined by register CR2F bits 3&2 PDATA35 Panel data These pins are used to provide the data interface to...
  • Page 93 Table 2-3 NM2160 Pin Descriptions Pin name Number Description RED This DAC analog output drives the CRT interface (Analog GREEN This DAC analog output drives the CRT interface (Analog BLUE This DAC analog output drives the CRT interface (Analog REXT DAC Current reference This pin is used as a current reference by (Analog the internal DAC.
  • Page 94 Table 2-3 NM2160 Pin Descriptions Pin name Number Description Activity Activity This pin when in input mode and asserted indicates the system activity. A high on this pin can be used to reset internal timers. This pin when in output mode is a General Purpose Output pin as defined by CR2F bits 5&4, which can be used to control the IMI chip for reduced EMI RTC32K/...
  • Page 95 Table 2-3 NM2160 Pin Descriptions Pin name Number Description VGADIS VGA Disable This pin when active disables all the accesses to the NM2160 controller, but maintains all the screen refreshes. GR12 bit-4 enables/disables this feature. NOTE: When driven by an external source, the swing on this pin should not be above LVDD DDC2BD DDC Data pin...

  • Page 96: Nma1

    NMA1 NMA1 is a single audio chip that integrates OPL3 FM and its DAC, 16bit Sigma-delta CODEC, MPU401 MIDI interface, and a 3D enhanced controller including all the analog components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play ISA 1.0a, and supports all the necessary features, i.e.

  • Page 97: Block Diagram

    2.4.2 Block Diagram Figure 2-4 NMA1 Block Diagram...

  • Page 98: Pin Diagram

    2.4.3 Pin Diagram Figure 2-5 NMA1 Pin Diagram...

  • Page 99: Pin Descriptions

    2.4.4 Pin Descriptions Conventions used in the pin description types: Input Pin with Pull up Resistor TTL-tri-state output pin Schmitt: TTL-Schmitt input pin Output Pin with Pull up Resistor Table 2-4 NMA1 Pin Descriptions Pin name Number Description ISA bus interface: 36 pins D7-0 Data Bus A15-0...
  • Page 100 Table 2-4 NMA1 Pin Descriptions Pin name Number Description ADFLTR Right input filter VOCOL Left voice output VOCOR Right voice output VOCIL Left voice input VOCIR Right voice input Miscellaneous pins: 14 pins SYEN External synthesizer enable input SYCS External synthesizer chip select output SYCLK External synthesizer clock input or ZV clock input SYLR...

  • Page 101: Philips 87C552 System Management Controller

    Philips 87C552 System Management Controller The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the 80C51. The 87C552 contains a 8kx8 a volatile 256x8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16- bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces...

  • Page 102: Block Diagram

    Extended temperature ranges OTP package available 2.5.2 Block Diagram Figure 2-6 87C552 Block Diagram...

  • Page 103: Pin Diagram

    2.5.3 Pin Diagram 60 AVSS P4.3/CMSR3 10 59 AVref+ P4.4/CMSR4 11 58 AVref– P4.5/CMSR5 12 57 P0.0/AD0 P4.6/CMT0 13 56 P0.1/AD1 P4.7/CMT1 14 55 P0.2/AD2 RST 15 54 P0.3/AD3 P1.0/CT0I 16 53 P0.4/AD4 P1.1/CT1I 17 52 P0.5/AD5 P1.2/CT2I 18 51 P0.6/AD6 P1.3/CT3I 19 50 P0.7/AD7 P1.4/T2 20...

  • Page 104: Pin Descriptions

    2.5.4 Pin Descriptions Table 2-5 87C552 Pin Descriptions Mnemonic Pin No. Type Name And Function Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode. STADC Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software).
  • Page 105 Table 2-5 87C552 Pin Descriptions Mnemonic Pin No. Type Name And Function P4.0-P4.7 7-14 Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: 7-12 CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. 13, 14 13, 14 CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

  • Page 106: Ns87338Vjg Super I/O Controller

    NS87338VJG Super I/O Controller The PC87338VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs, and an IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super l/O family.
  • Page 107 The Bidirectional Parallel Port: Enhanced Parallel Port(EPP) compatible Extended Capabilities Port(ECP) compatible, including level 2 support Bidirectional under either software or hardware control Compatible with ISA, and EISA, architectures Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk Drive(FDD) Includes protection circuit to prevent damage to the parallel port when a connected printer is powered up or is operated at a higher voltage...

  • Page 108: Block Diagram

    2.6.2 Block Diagram Config. Serial Serial Interrupt Interrupt Inputs Interface Interface Interface UART Configuration UART + IrDA/HP & Sharp IR Registers (16550 or 16450) (16550 or 16450) Floppy Disk Floppy Controller with Drive Digital Data Interface Separator Floppy Drive (Enhabced 8477) General IEEEE1284 Power...

  • Page 109: Pin Diagram

    2.6.3 Pin Diagram Figure 2-9 NS87338VJG Pin Diagram...

  • Page 110: Pin Description

    2.6.4 Pin Description Table 2-6 NS87338VJG Pin Descriptions Description A15-A0 67, 64, Address. These address lines from the microprocessor determine 62-60, which internal register is accessed. A0-A15 are don't cares during 29, 19- DMA transfer. /ACK Parallel Port Acknowledge. This input is pulsed low by the printer to indicate that it has received the data from the parallel port.
  • Page 111 Table 2-6 NS87338VJG Pin Descriptions Description /CTS1, 72, 64 UARTs Clear to Send. When low, this indicates that the modem or /CTS2 data set is ready to exchange data. The /CTS signal is a modem status input. The CPU tests the condition of this /CTS signal by reading bit 4 (CTS) of the Modem Status Register (MSR) for the appropriate serial channel.
  • Page 112 Table 2-6 NS87338VJG Pin Descriptions Description /DR1 FDC Drive Select 1. This pin offers an additional Drive Select signal (PPM Mode) in PPM Mode when PNF = 0. It is drive select 1 when bit 4 of FCR is 0. It is drive select 0 when bit 4 of FCR is 1. This signal is active low. /DR23 FDC Drive 2 or 3.
  • Page 113 Table 2-6 NS87338VJG Pin Descriptions Description /HDSEL FDC Head Select. This output determines which side of the FDD is (Normal Mode) accessed. Active selects side 1, inactive selects side 0. /HDSEL FDC Head Select. This pin offers an additional Head Select signal in (PPM Mode) PPM Mode when PNF = 0.
  • Page 114 Table 2-6 NS87338VJG Pin Descriptions Description IRTX Infrared Transmit. Infrared serial data output. Software configuration selects either IrDA or Sharp-IR protocol. This pin is multiplexed with SOUT2/BOUT/CFG0. Master Reset. Active high output that resets the controller to the idle state and resets all disk interface outputs to their inactive states. The DOR, DSR, CCR, Mode command, Configure command, and Lock command parameters are cleared to their default values.
  • Page 115 Table 2-6 NS87338VJG Pin Descriptions Description /RI1 68, 60 UARTs Ring Indicator. When low, this indicates that a telephone ring /RI2 signal has been received by the modem. The /RI signal is a modem status input whose condition is tested by the CPU by reading bit 6 (RI) of the Modem Status Register (MSR) for the appropriate serial channel.
  • Page 116 Table 2-6 NS87338VJG Pin Descriptions Description /TRK0 FDC Track 0. This input indicates the controller that the head of the (Normal Mode) selected floppy disk drive is at track zero. /TRK0 FDC Track 0. This pin gives an additional Track 0 signal in PPM (PPM Mode) Mode when PNF = 0.

  • Page 117: Cl-Pd6832: Pci-To-Cardbus Host Adapter

    CL-PD6832: PCI-to-CardBus Host Adapter The CL-PD6832 is a single-chip PC Card host adapter solution capable of controlling two fully independent CardBus sockets. The chip is compliant with PC Card Standard, PCMCIA 2.1, and JEDIA 4.1 and is optimized for use in notebook and handheld computers where reduced form factor and low power consumption are critical design objectives.

  • Page 118: Pin Diagram

    208-pin PQFP 2.7.2 Pin Diagram Figure 2-10 CL-PD6832 Pin Diagram 2.7.3 Pin Descriptions The following conventions apply to the pin description tables: A pound sign (#) at the end of a pin name indicates an active-low signal for the PCI bus. A dash (-) at the beginning of a pin name indicates an active-low signal for the PCMCIA bus.
  • Page 119 An asterisk (*) at the end of a pin name indicates an active-low signal that is a general- interface for the CL-PD6832. ‡ A double-dagger superscript ( ) at the end of the pin name indicates signals that are used for power-on configuration switches.

  • Page 120: Cl-Pd6832 Pin Descriptions

    The following table lists the pin descriptions Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number Power PCI Bus Interface Pins AD[31:0] 4-5, 7-12, 16-20, PCI Bus Address Input / Data 22-24, 38-43, 45- Input/Outputs: These pins connect to PCI bus 46, 48 49, 51-56 signals AD[31:0].
  • Page 121 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number Power PERR# Parity Error: The CL-PD6832 drives this output active (low) if it detects a data parity error during a write phase. SERR# System Error: This output is pulsed by the CL- PD6832 to indicate an address parity error.
  • Page 122 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number Power SOUT#/ Serial Interrupt Output / PCI Bus Interrupt C INTC#/ / Serial IRQ Load: In PCI Interrupt Signaling ISLD mode, this output can be used as an interrupt output connected to the PCI bus INTC# interrupt line.
  • Page 123 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. Pin No. Power (socke (socket t A) Socket Interface Pins -REG/ 2 or 3 Register Access: In Memory Card CC/BE3# Interface mode, this output chooses between attribute and common memory. In l/O Card Interface mode, this signal is active (low) for non DMA transfers and high for DMA transfers.
  • Page 124 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. Pin No. Power (socke (socket t A) A13/ 2 or 3 PCMCIA socket address 13 output. In CPAR CardBus mode, this pin is the Cardbus PAR signal. A12/ 2 or 3 PCMCIA socket address 12 output.
  • Page 125 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. Pin No. Power (socke (socket t A) -OE/ 2 or 3 Output Enable: This output goes CAD11 active(low) to indicate a memory read from the PCMCIA socket to the CL-PD6832. In CardBus mode, this pin is the Cardbus address/data bit 11.
  • Page 126 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. Pin No. Power (socke (socket t A) -CD[2:1]/ 126, 61 202, I-PU Card Detect: These inputs indicate to the CCD[2:1]# CL-PD6832 that a card is in the socket. They are internally pulled high to the voltage of the +5V power pin.
  • Page 127 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. Pin No. Power (socke (socket t A) BVD1/ I-PU 2 or 3 Battery Voltage Detect 1 / Status Change -STSCHG/ / Ring Indicate: In Memory Card Interface -RI/ mode, this input serves as the BVD1 -CSTSCHG (battery-dead status) input.
  • Page 128 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number Power Power Control and General Interface Pins SPKR_OUTt I/O- Speaker Output: This output can be used as a digital output to a speaker to allow a system to support PCMCIA card fax/modem/voice and audio sound output.
  • Page 129 Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number Power SLATCH/ I/O- 2 or3 Serial Latch / System Management Bus SMBLCKt Clock: This pin serves as output pin SLATCH when used with the serial interface of Texas Instruments' TPS2202AIDF socket power control chip, and serves as a bidirectional pin SMBCLK when used with Intel's System Management Bus used by Maxim's socket...

  • Page 130: Ambit T62.036.C Dc-Dc Converter

    Ambit T62.036.C DC-DC Converter This T62.036.C DC-DC converter supplies multiple DC(5V, 3,3V, 12V) output to system, and also supplies the battery charge current (0~3.5A). The total inputs from the notebook would be limited by the total output of 65 watts maximum. 2.8.1 Pin Diagram T62.036.C...
  • Page 131 Table 2-8 T62.036.C Pin Descriptions Pin Name Pin Type Pin No. Description indicate the current drawn from the AC adapter or other power source such as docking station power supply. This level is 2 Amps per volt nominal. The source impedance is less than 1K . CHARGSP Analog input from the system board to limit the total current consumed by the system from the AC adapter.

  • Page 132: Ambit Dc-Ac Inverter

    Ambit DC-AC Inverter This notebook uses two kinds of DC-AC inverters: One (T62.088.C) is designed for the 13.3-inch TFT (LG LP133X1) LCD, the other (T62.055.C) for the 12.1-inch TFT (IBM ITSV50D) LCD. 2.9.1 T62.055C 2.9.1.1 Pin Diagram T62.055.C Figure 2-12 T62.055.C Pin Diagram 2.9.1.2 Pin Descriptions...

  • Page 133: T62.088C

    Table 2-9 T62.055.C Pin Descriptions Pin Name Pin Type Pin No. Descriptions BATTLED This signal is an open collector sink signal to drive LED2. The LED current is limited by a series resistor of 1K . BMCVCC This a 5 volt supply for powering the LEDs. It should not be used for any other purpose.
  • Page 134 Table 2-10 T62.088.C Pin Descriptions Pin Name Pin Type Pin No. Descriptions ADVDD This is a 5-volt power line for the analog circuits and display LEDs on the inverter board. MIC_OUT Microphone preamplifier circuit output AUDGND Microphone circuit return ground 4, 5 System ground SGND...
  • Page 135 C h a p t e r C h a p t e r BIOS Setup Information The computer BIOS setup utility allows you to configure the computer and its hardware settings. The computer comes correctly configured, and you do not need to run the BIOS setup utility to use the computer.

  • Page 136: About My Computer

    About My Computer Selecting About My Computer presents you with two screens of details about the computer and its peripherals. These screens are for information only; you cannot change the settings on these screens. The following table tells you what each of the items on the About My Computer screens are.

  • Page 137: System Configuration

    System Configuration Selecting System Configuration presents a Basic System Configuration screen, where you can change several items in your computer’s configuration. Press to move from one item to another, and to change settings. Press F1 to get help on a selected item. Press Esc to exit the Basic System Configuration screen and return to the main BIOS Utility screen.

  • Page 138: Internal Speaker

    3.2.6 Internal Speaker This parameter lets you enable or disable the internal speaker. The default setting is Enabled. Tip: You can also toggle the speaker on and off by pressing the speaker hot key combination Fn+F7. 3.2.7 Silent Boot When set to Enabled, the computer shows the computer logo onscreen and hides the POST routine messages.

  • Page 139: Advanced System Configuration

    Advanced System Configuration For advanced users, the System Configuration menu item contains two hidden pages that allow you to view and configure more technical aspects of the computer. Caution: The computer is already tuned for optimum performance and you should not need to access these advanced screens.

  • Page 140: Onboard Communication Ports

    Advanced PIO Mode. Advanced PIO (Programmed Input/Output) Mode enhances drive performance by optimizing the hard disk timing. The available values are: Auto and Mode 0. The default setting is Auto. Hard Disk 32 Bit Access. This parameter allows your hard disk to use 32-bit access. The available values are: Auto and Disabled.

  • Page 141: Reset Pnp Resources

    3.3.6 Reset PnP Resources The system resources are already properly configured. If resource conflicts arise, you can set this parameter to Yes to reset and reallocate PnP resources, after which the BIOS automatically resets this parameter to No, which is the default setting.

  • Page 142: Power Saving Options

    Power Saving Options Selecting Power Saving Options on the BIOS Utility main screen presents a screen that allows you to adjust several power-saving settings. 3.4.1 When Lid is Closed The computer’s lid switch acts as its power switch: opening the display wakes up the computer, closing the display puts it to sleep.

  • Page 143: Resume On Schedule

    3.4.5 Resume On Schedule When this parameter is set to Enabled, the computer resumes from suspend-to-memory mode at the specified date and time. Enabling this option overrides the suspend-to-disk function. The Resume Date and Resume Time parameters let you set the date and time for the resume operation.

  • Page 144: System Security

    System Security When you select System Security from the BIOS Utility main screen, a screen appears that allows you to set security options. Important! If a password is currently present, the system prompts you to input the password before entering the System Security screen.

  • Page 145: Diskette Drive Access Control

    3.5.2 Diskette Drive Access Control This parameter allows you to control the read and write functions of the floppy drive. The available options. are: Normal, Write Protect, and Disabled. The default is Normal. With this parameter set to Normal, the floppy drive functions normally. When the parameter is set to Write Protect, all write functions to the floppy drive are disabled, but you can still read from a disk in the floppy drive.

  • Page 146: Reset To Default Settings

    Reset To Default Settings When you select the Reset To Default Settings from the BIOS Utility main screen, a dialog box appears asking you to confirm that you want to reset all settings to their factory defaults.

  • Page 147: Chapter 4 Disassembly And Unit Replacement

    C h a p t e r C h a p t e r Disassembly and Unit Replacement This chapter contains step-by-step procedures on how to disassemble the notebook computer for maintenance and troubleshooting. To disassemble the computer, you need the following tools: Wrist grounding strap and conductive mat for preventing electrostatic discharge Flat-bladed screwdriver Phillips screwdriver...

  • Page 148: Removing The Battery Pack

    Figure 4-1 Removing the Battery Pack Removing all power sources from the system prevents accidental short circuit during the disassembly process.

  • Page 149: Connector Types

    4.1.2 Connector Types There are two kinds of connectors on the main board: Connectors with no locks Unplug the cable by simply pulling out the cable from the connector. Connectors with locks You can use a plastic stick to lock and unlock connectors with locks. The cables used here are special FPC (flexible printed-circuit) cables, which are more delicate than normal plastic-enclosed cables.

  • Page 150: Disassembly Sequence

    Connectors mentioned in the following procedures are assumed to be no-lock connectors unless specified otherwise. 4.1.3 Disassembly Sequence The disassembly procedure described in this manual is divided into eight major sections: Section 4.2: Removing the module Section 4.3: Replacing the hard disk drive Section 4.4: Replacing memory Section 4.5:...

  • Page 151: Disassembly Flow

    The following diagram details the disassembly flow. Figure 4-3 Disassembly Flow...

  • Page 152: Removing The Module

    Removing the Module If you are going to disassemble the unit, it is advisable to remove the module first before proceeding. Follow these steps to remove the module: Slide out and hold the module release button. Press the module release latch and slide out the module. Module Release Button Module Release...

  • Page 153: Replacing The Hard Disk Drive

    Replacing the Hard Disk Drive Follow these steps: Turn the computer over to access the base. Remove the two screws from the hard disk drive bay cover and remove the cover. Figure 4-5 Removing the Hard Disk Drive Bay Cover Lift up (1), then pull out the hard disk drive;...

  • Page 154: Replacing Memory

    Replacing Memory The memory slots (SIMM1 and SIMM2) are accessible via the memory door at the base of the unit. Follow these steps to install memory module(s): Turn the computer over to access the base. Remove the screws from the memory door and remove the door. Figure 4-7 Installing a Memory Module Remove the memory module(s) from its shipping container.
  • Page 155 You must run the Sleep Manager utility after installing additional memory in order for the 0V Suspend function to operate in your system. If Sleep Manager is active, it will auto-adjust the partition/file on your notebook for 0V Suspend to function properly. If you are using an operating system other than Windows 95 or DOS, you may need to re-partition your hard disk drive to allow for the additional memory.

  • Page 156: Removing The Keyboard

    Removing the Keyboard Follow these steps to remove the keyboard: Slide out the two display hinge covers on both sides of the notebook. Figure 4-9 Removing the Display Hinge Covers Pull out (first from the edges) and remove the center hinge cover. Figure 4-10 Removing the Center Hinge Cover...

  • Page 157: Lifting Out The Keyboard

    Lifting out the keyboard takes three steps — (a) lifting up the keyboard, (b) rotating the keyboard to one side, and (c) pulling out the keyboard in the opposite direction. Figure 4-11 Lifting Out the Keyboard Flip the keyboard over and unplug the keyboard connectors (CN4, CN2) to remove the keyboard.

  • Page 158: Replacing The Cpu

    Replacing the CPU Follow these steps to remove the CPU module. Remove six screws that secure the CPU heat sink to the chassis. Figure 4-13 Removing the CPU Heat Sink Remove one screw and pull up the CPU module. (CN8, CN12) When inserting a CPU module, take note of the female and male connectors on the CPU module.

  • Page 159: Removing The Display

    Removing the Display Follow these steps to remove the display module. Remove the two screws that secure the display cable to the motherboard. Then unplug the display cable (CN6). Figure 4-15 Unplugging the Display Cable Remove the four display hinge screws. Detach the display from the main unit and set aside. Figure 4-16 Removing the Display Hinge Screws and Removing the Display...

  • Page 160: Disassembling The Housing

    Disassembling the Housing This section discusses how to disassemble the housing, and during its course, includes removing and replacing of certain major components like the hard disk drive, memory and the main board. 4.8.1 Detaching the Lower Housing from the Inside Assembly To detach the lower housing from the inside assembly, turn the unit over and remove seven (7) base screws.

  • Page 161: Detaching The Upper Housing From The Inside Assembly

    4.8.2 Detaching the Upper Housing from the Inside Assembly Follow these steps: Remove three screws in the battery bay. Figure 4-18 Removing the Battery Bay Screws Turn the unit back over and remove two screws close to the back part of the unit. Then snap out the upper part of the housing —...

  • Page 162: Removing The Touchpad

    4.8.3 Removing the Touchpad Follow these steps to remove the touchpad: Unplug the touchpad connector (CN5). Pull up and remove the touchpad. Figure 4-20 Removing the Touchpad 4.8.4 Removing the Main Board Follow these steps to remove the main board from the inside assembly. Unplug the speaker connectors (CN17 and CN23), and the battery pack connector (CN21).

  • Page 163: Removing The Main Board

    Remove four screws to remove the main board from the inside assembly. Figure 4-22 Removing the Main Board Remove the charger board (CN19 and CN20) and the multimedia board (CN10 and CN7) from the main board. Figure 4-23 Removing the Charger Board and Multimedia Board...

  • Page 164: Removing The Pc Card Slots

    The PC card slot module is usually part of the main board spare part. This removal procedure is for reference only. To remove the PC card slot module, remove two screws. Figure 4-24 Removing the PC Card Slots...

  • Page 165: Disassembling The Display

    Disassembling the Display Follow these steps to disassemble the display: Remove the teardrop-shaped LCD bumpers at the top of the display and the long bumper on the LCD hinge. Figure 4-25 Removing the LCD Bumpers Remove four screws on the display bezel. •...

  • Page 166: Removing The Display Bezel

    Pull out and remove the display bezel by pulling on the inside of the bezel sides. Figure 4-27 Removing the Display Bezel Remove the four display panel screws, and unplug the inverter and display panel connectors. Then tilt up and remove the display panel. ‘...

  • Page 167: Removing The Display Cable Assembly

    Remove the two display assembly screws and unplug the display cable connector from the display cable assembly. Then remove the LCD inverter and ID boards. Screw list: ‘ M2.5L6 (bind head) x2 ‘ ‘ LCD Inverter DC-AC inverter Figure 4-29 Removing the Display Cable Assembly...

  • Page 168: Model Number Definition

    TravelMate 7100 VU - W X Y Z Z: Acer or TI logo TI logo Blank: Acer logo or base unit for uniload Y: Keyboard language version Swiss for ANW with US power cord US for standard model with US power cord...

  • Page 169: Exploded View Diagram List

    A p p e n d i x A p p e n d i x Exploded View Diagram This appendix includes exploded view diagrams of the notebook. Table B-1 Exploded View Diagram List Description System assembly 12.1-inch LCD Module assembly (Acer) 12.1-inch LCD Module assembly (TI)

  • Page 173: Spare Parts List

    LCD Module for Acer INVERTER T62.055.C 970 19.21030.041 MICROPHONE 54DB KUC8723-030839 23.42009.001 PLT NAME(7100) PC 7100 ACER 40.46805.101 FOR ACER C.A FPC 12.1 (DOUBLE SHD) 970T 50.42A05.001 LCD ITSV50D 12.1" TFT IBM 970T 56.0742A.011 ASSY LCD PNL (12.1") 970T 60.42A13.022...
  • Page 174 Table C-1 Spare Parts List Ref# of Description Acer part no. Comment/location Min. Qty exploded diagram Lower Case C04, C05 ASSY LOWER CASE 970T 60.42A03.001 ASSY DOOR CARDBUS SUS301 970 60.46806.002 Chassis SPK T023S03T0013 D23 W/CAB65MM 23.40015.031 CABLE ASSY 8P #24 BTY 970 50.46807.001...
  • Page 175 56.01051.072 ASSY FDD MODULE 050 970 6M.42A08.001 65.46802.001 ASSY FDD MODULE 050 970 * 1 PCS FDD-931 91.46805.001 FDD MODULE ACER COLOR 050 FDD-963 91.46805.002 FDD MODULE COLOR 076 CABLE ASSY FPC 44P 43MM 50.42003.002 (HDD CABLE) HDD 3240MB 2.5*IBM/DTCA23240...
  • Page 176 HDD 4090MB 2.5" IBM DTLA 56.02834.071 ASSY HDD COVER 970T 60.42A01.001 ASSY HDD DOOR 970T 60.42A02.001 Docking ADS-231(TM7100) MINI DOCKING 91.42A27.001 SYSTEM BD ACER DOCK 970T 55.42A041.021 FOR ADS-231 MEDIA BOARD ACER DOCK 970T 55.42A02.031 FOR ADS-231 ADS-131 91.46828.021 ACERDOCK-III ACER 050 CLR ADS-160 91.46828.022...

  • Page 177: Post Checkpoint List

    A p p e n d i x A p p e n d i x BIOS POST Checkpoints This appendix lists the POST checkpoints of the notebook BIOS. Table E-1 POST Checkpoint List Checkpoint Description Determines if the current booting procedure is from cold boot (press reset button or turn the system on), from warm boot (press Ctrl +Alt +Del).
  • Page 178 Note: If system has any display card, here it should be initialized via its I/O ROM or corresponding initialization program. VGA BIOS POST. Enables video shadow RAM Displays Acer (or OEM) logo (if necessary) Displays Acer copyright message (if necessary) Displays BIOS serial number Memory testing...
  • Page 179 Table E-1 POST Checkpoint List Checkpoint Description Enables UIE, then checks RTC update cycle Note: The RTC executes an update cycle per second. When the UIE is set, an interrupt (IRQ8) occurs after every update cycle and indicates that over 999ms are available to read valid time and date information.
  • Page 180 Table E-1 POST Checkpoint List Checkpoint Description Clear memory buffer used for POST Select boot device Shutdown 5 Shutdown A Shutdown B...
  • Page 181 A p p e n d i x A p p e n d i x Exploded View Diagram This appendix includes exploded view diagrams of the notebook. Table B-1 Exploded View Diagram List Description System assembly 12.1-inch LCD Module assembly (Acer) 12.1-inch LCD Module assembly (TI)

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