Table 34. DMA I/O address map
Address (hex)
Description
00CE
Channel 7, Transfer Count register
00D0
Channels 4–7, Read Status/Write Command
register
00D2
Channels 4–7, Write Request register
00D4
Channels 4–7, Write Single Mask register bit
00D6
Channels 4–7, Mode register (write)
00D8
Channels 4–7, Clear byte pointer (write)
00DA
Channels 4–7, Master clear (write)/temp (read)
00DC
Channels 4–7, Clear Mask register (write)
00DE
Channels 4–7, Write All Mask register bits
00DF
Channels 507, 8- or 16-bit mode select
PCI configuration space map
Table 35. PCI configuration space map
Bus number (hex)
Device number (hex) Function number (hex) Description
00
00
00
00
00
01
00
01
00
01
00
01
00
01
00
02
00
05
01
00
00
01
00
01
02
03
04
00
00
00
Bits
Byte pointer
00–15
Yes
00–07
00–02
00–02
00–07
N/A
00–07
00–03
00–03
00–07
Host Bridge
IDE controller
ISA Bridge
Ethernet network
Universal Serial Bus
Universal Serial Bus
Audio Multimedia
PCI to PCI Bridge
Ethernet or modem
VGA Graphics
Appendix B. System address maps
37