Memory Test Menu - HP D6030A - NetServer - E50 User Manual

Appendix B

Memory Test Menu

The Memory Test Menu includes tests that exercise all aspects of the storage
media and key memory locations of the system. The functionality of the boot
ROM, parity over the whole memory space, patterns, addressing, refresh
functions, and the data bus have specific tests included in the menu. Specialized
testing for memory caching, performance, and the proprietary Pentium II L2
Cache are included.
BIOS ROM Test
The BIOS ROM test checks the data path of the BIOS ROM and also assures that
the ROM is write-protected.
Parity Test
This test reads all memory locations and checks for parity errors in the entire
memory space. When the CPU accesses a memory location that has a parity
error, a bit is set in a specific register and an NMI (non-maskable interrupt) is
generated. DiagTools' parity test captures the interrupt so that the system does
not crash even when a parity error is encountered. It then reads the entire
memory region for errors.
Pattern Test
This test performs a comprehensive read/write test on entire memory space, using
worst-case bit patterns such as AA55. This test will identify most memory
problems.
Extended Pattern Test
This test performs a comprehensive write/read test on extended memory using
several different scientifically proven worst-case test patterns.
Walking 1's Test
Walking 1's test writes a walking 1s pattern in memory, i.e. it first writes 1, then
2,4,8,16 etc., so that in the written data, only one bit is on at a time.
Walking 0's Test
Walking 0's test writes a walking 0s pattern in memory, i.e. it first writes FE,
then FD,FB etc., so that in the written data, only one bit is 0 at a time.
Random Memory Test
This test uses a pseudo-random number generator to generate random addresses
spread over the whole memory area, and then writes random data to the location,
reads it back and compares the data read with the data written.
Test Descriptions
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