Interface
attention: The device responds to this command with the result of power-on
At command issuance (I/O registers setting contents)
1F7
(CM)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(FR)
H
At command completion (I/O registers contents to be read)
1F7
(ST)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(ER)
H
*1
This register indicates X'00' in the LBA mode.
5-56
Table 5.6 Diagnostic code
Code
Result of diagnostic
X'01'
No error detected.
X'02'
HDC diagnostic error
X'03'
Buffer diagnostic error
X'04'
SRAM diagnostic error
X'05'
MPU diagnostic error
X'07'
ROM sum check error
X'08'
Failure of HDC PVT cell
X'09'
Failure of HDC DE/ECC
X'8x'
Failure of device 1
diagnostic test.
1
0
0
x
x
x
xx
xx
xx
xx
xx
Status information
x
x
x
xx
xx
01
(*1)
H
01
H
Diagnostic code
1
0
0
0
DV
Head No. /LBA MSB]
DV
Head No. /LBA MSB]
0
C141-E171-03EN