Intel DUAL-CORE - SPECIFICATION UPDATE REV 010 Specification page 49

Errata
AN99. Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to
both code #DB (Debug Exception) and code Segment Limit Violation #GP (General
Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of
the following conditions are met:
A PDE (Page Directory Entry) is modified without invalidating the corresponding
•
TLB (Translation Look-aside Buffer) entry
Code execution transitions to a different code page such that both
•
 The target linear address corresponds to the modified PDE
 The PTE (Page Table Entry) for the target linear address has an A (Accessed)
One of the following simultaneous exception conditions is present following the
•
code transition
 Code #DB and code #PF
 Code Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before code Segment
Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the
AN100. Performance Monitoring Event MISALIGN_MEM_REF May Over Count
Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the
number of memory accesses that cross an 8-byte boundary and are blocked until
retirement. Due to this erratum, the performance monitoring event
MISALIGN_MEM_REF also counts other memory accesses.
Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The extent
of the over counting depends on the number of memory accesses retiring while the
counter is active.
Workaround: None Identified
Status:
For the steppings affected, see the
Specification Update
bit that is clear
Summary Tables of Changes.
Summary Tables of Changes.
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