Intel DUAL-CORE - SPECIFICATION UPDATE REV 010 Specification page 25

Errata
AN24. Disabling of Single-step on Branch Operation May Be Delayed
following a POPFD Instruction
Problem: Disabling of Single-step On Branch Operation may be delayed, if the following
conditions are met:
"Single Step On Branch Mode" is enabled (DebugCtlMSR.BTF and EFLAGS.TF are set)
POPFD used to clear EFLAGS.TF
A jump instruction (JMP, Jcc, etc.) is executed immediately after POPFD
Implication: Single-step On Branch mode may remain in effect for one instruction after the POPFD
instruction disables it by clearing the EFLAGS.TF bit.
Workaround: There is no workaround for Single-Step operation in commercially available software.
The workaround for custom software is to execute at least one instruction following
POPFD before issuing a JMP instruction.
Status: For the steppings affected, see the
AN25. Performance Monitoring Counters That Count External Bus Events
May Report Incorrect Values after Processor Power State Transitions
Problem:
Performance monitoring counters that count external bus events operate when the
processor is in the Active state (C0). If a processor transitions to a new power state,
these Performance monitoring counters will stop counting, even if the event being
counted remains active.
Implication: After transitioning between processor power states, software may observe incorrect
counts in Performance monitoring counters that count external bus events.
Workaround: None identified.
Status: For the steppings affected, see the
Specification Update
Summary Tables of Changes.
Summary Tables of Changes.
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