Intel DUAL-CORE - SPECIFICATION UPDATE REV 010 Specification page 13

Summary Tables of Changes
Number D0
AN81 X
AN82
AN83
AN84
AN85
AN86
AN87
AN88
AN89
AN90
AN91
AN92
AN93
AN94
AN95
AN96
AN97
AN98
AN99
AN100
AN101
AN102
AN103
AN104
Specification Update
M0 Plans
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
X No Fix
Count Some Transitions
No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
X
May Be Incorrect
No Fix Erratum Removed
No Fix Some Bus Performance Monitoring Events May Not Count Local
X
Events under Certain Conditions
X No Fix EIP May Be Incorrect after Shutdown in IA-32e Mode
No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs
X
May Be Incorrect
No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced
X
before Higher Priority Interrupts/Exceptions
No Fix LBR, BTS, BTM May Report a Wrong Address when an
X
Exception/Interrupt Occurs in 64-bit Mode
No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or
X
Equal to 2
No Fix IRET under Certain Conditions May Cause an Unexpected Alignment
X
Check Exception
X No Fix PMI May Be Delayed to Next PEBS Event
X No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP
No Fix B0-B3 Bits in DR6 May Not Be Properly Cleared after Code
X
Breakpoint
No Fix Performance Monitor SSE Retired Instructions May Return Incorrect
X
Values
No Fix Performance Monitoring Events for L1 and L2 Miss May Not Be
X
Accurate
No Fix Erratum Removed
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
No Fix
X
Counted Incorrectly for PMULUDQ Instruction
Storage of PEBS Record Delayed Following Execution of MOV SS or
No Fix
X
STI
No Fix Updating Code Page Directory Attributes without TLB Invalidation
X
May Result in Improper Handling of Code #PF
No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over
X
Count
No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
X
Prevent Triggering of the Monitoring Hardware
No Fix A Memory Access May Get a Wrong Memory Type Following a #GP
X
due to WRMSR to an MTRR Mask
No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
X
Information
No Fix Erratum Removed
ERRATA
48
May Terminate Early
13