Intel DUAL-CORE - SPECIFICATION UPDATE REV 010 Specification page 27

Errata
AN29. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFh)
Problem:
Performance monitoring for Event CFH normally increments on saturating SIMD
instruction retired. Regardless of DR7 programming, if the linear address of a retiring
memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the CFH counter may be incorrectly incremented.
Implication: The value observed for performance monitoring count for saturating SIMD instructions
retired may be too high. The size of error is dependent on the number of occurrences
of the conditions described above, while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the
AN30. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM Instruction before Restoring the Architectural
State from SMRAM
Problem: The Resume from System Management Mode (RSM) instruction does not flush global
pages from the Data Translation Look-Aside Buffer (DTLB) prior to reloading the saved
architectural state.
Implication: If SMM turns on paging with global paging enabled and then maps any of linear
addresses of SMRAM using global pages, RSM load may load data from the wrong
location.
Workaround: Do not use global pages in system management mode.
Status: For the steppings affected, see the
Specification Update
Summary Tables of Changes.
Summary Tables of Changes.
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