Intel DUAL-CORE - SPECIFICATION UPDATE REV 010 Specification page 11

Summary Tables of Changes
Number D0
AN35 X
AN36
AN37 X
AN38 X
AN39 X
AN40 X
AN41 X
AN42
AN43
AN44 X
AN45 X
AN46 X
AN47 X
AN48 X
AN49 X
AN50 X
AN51 X
AN52 X
AN53 X
AN54 X
AN55
AN56 X
AN57 X
Specification Update
M0 Plans
Programming the Digital Thermal Sensor (DTS) Threshold May
X No Fix
Cause Unexpected Thermal Interrupts
Erratum removed
X No Fix The Processor May Report a #TS Instead of a #GP Fault
Fixed BTS Message May be Lost when the STPCLK# Signal is Active
Certain Performance Monitoring Counters Related to Bus, L2 Cache
Fixed
and Power Management are Inaccurate
A Write to an APIC Register Sometimes May Appear to Have Not
X No Fix
Occurred
IO_SMI Indication in SMRAM State Save Area May be Set
X No Fix
Incorrectly
Erratum removed
Erratum removed
Fixed Logical Processors May Not Detect Write-Back (WB) Memory Writes
X No Fix LER MSRs May be Incorrectly Updated.
SYSENTER/SYSEXIT Instructions Can Implicitly Load "Null Segment
Fixed
Selector" to SS and CS Registers
Writing the Local Vector Table (LVT) when an Interrupt is Pending
X No Fix
May Cause an Unexpected Interrupt
Using 2M/4M pages When A20M# Is Asserted May Result in
X No Fix
Incorrect Address Translations
Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and
Fixed IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural
Performance Monitoring) Specification
Premature Execution of a Load Operation Prior to Exception Handler
X No Fix
Invocation
Performance Monitoring Events for Retired Instructions (C0H) May
X No Fix
Not Be Accurate
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
X No Fix
When Execute Disable Bit is Not Supported
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present
Fixed (P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code
Fixed
(SMC) Event May Cause Unexpected Behavior
No Fix Erratum Removed
X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware
Writing Shared Unaligned Data that Crosses a Cache Line without
X No Fix Proper Semaphores or Barriers May Expose a Memory Ordering
Issue
ERRATA
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