Agp Timing Settings - JETWAY V623DMR1A User Manual

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
DRAM Timing
x DRAM CAS Latency
Bank Interleave
RAS Precharge Time
RAS Active Time
RAS to CAS Delay
DRAM Command Rate
↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T, 2.5T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T.

3-6-2 AGP Timing Settings

DRAM Timing Setting
By SPD
2.5
4 Banks
3T
6T
3T
2T
F6:Optimized Defaults
26
Item Help
Menu Level >>
When set to "Auto",
BIOS will program this
Timing mainly by the
SPD method. SPD means
"Serial Presence
Detect", which enables
the BIOS to access
the manufacturer
settings stored in
DRAM module.
F1:General Help
F7:Standard Defaults