Agp Timing Settings; Pci Timing Settings - JETWAY P4M2PRO-P User Manual

3-6-2 AGP Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
AGP Aperture Size
AGP Transfer Mode
AGP Driving Control
AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
AGP 3.0 Calibration Cycle
VGA Share Memory Size
Direct Frame Buffer
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.

3-6-3 PCI Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to PCI Write Buffer
PCI Delay Transaction
VLink Mode Selection
VLink 8X Support
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
AGP Timing Settings
64M
4X
Auto
AA
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
64M------
Disabled
F6:Optimized Defaults
PCI Timing Settings
Disabled
Disabled
Enabled
Enabled
Mode 1
Enabled
F6:Optimized Defaults
35
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F7:Standard Defaults
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F7:Standard Defaults