Pci Timing Settings; Integrated Peripherals - JETWAY V623DMR1A User Manual

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
AGP Aperture Size
AGP Mode
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
VGA Share Memory Size
↑↓→← Move Enter:Select
F5:Previous Values

3-6-3 PCI Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to PCI Post Write
PCI Delay Transaction
↑↓→← Move Enter:Select
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.

3-7 Integrated Peripherals

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
OnChip IDE Function
OnChip Device Function
OnChip SIO Function
Init Display First
↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
OnChip IDE Function
AGP Timing Settings
64MB
4X
Disabled
Disabled
Disabled
Enabled
Enabled
32MB
+/-/PU/PD:Value F10:Save ESC:Exit
F6:Optimized Defaults
PCI Timing Settings
Disabled
Disabled
Disabled
Enabled
+/-/PU/PD:Value F10:Save ESC:Exit
F6:Optimized Defaults
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
F6:Optimized Defaults
27
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults
Item Help
Menu Level >
F1:General Help
F7:Standard Defaults