Agp Timing Settings; Pci Timing Settings - JETWAY PT800DB - REV 1.0 User Manual

CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the
DRAM timing. The settings are: 2T and 2.5T.
3-6-2

AGP Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
AGP Transfer Aperture Size
AGP Transfer Mode
AGP Driving Control
* AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
AGP Delay Transaction
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.
3-6-3

PCI Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to AGP Post Write
PCI Delay Transaction
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
AGP Timing Settings
64M
4X
Auto
DA
Disabled
Enabled
Enabled
Disabled
Disabled
Disabled
F6:Optimized Defaults
PCI Timing Settings
Disabled
Disabled
Enabled
Disabled
F6:Optimized Defaults
28
Item Help
Menu Level >>
F7:Standard Defaults
Item Help
Menu Level >>
F7:Standard Defaults