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NXP Semiconductors LPC5411 Series User Manual

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UM10914

LPC5411x User manual

Rev. 2.0 — 9 May 2018

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LPC5411x User Manual

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Cortex

-M4, Arm Cortex

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-M0+, microcontroller, USB FS device

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Page 1 UM10914 LPC5411x User manual Rev. 2.0 — 9 May 2018 User manual Document information Info Content ® ® ® Keywords Cortex -M4, Arm Cortex -M0+, microcontroller, USB FS device Abstract LPC5411x User Manual...
Page 2 UM10914 NXP Semiconductors LPC5411x User manual Revision history Date Description • 20180509 In several chapters, the order of some subsections was altered to make the order more uniform throughout the User Manual: GPIO, CTIMER, RTC, SYSTICK, UTICK, USB device controller, Flexcomm, I2C, and I2S.
Page 3 UM10914 NXP Semiconductors Chapter : Revision history …continued Date Description • 20171208 Changed the notation for ADC sample rates throughout the manual: megasamples per second to Msps. • Added a note to the description of ISP commands that use “RAM” to clarify that this refers to on-chip RAM.
Page 4 UM10914 NXP Semiconductors LPC5411x User manual Revision history …continued Date Description • 20171208 Corrected the description of the WAKERX bit in the FIFOCFG register in Chapter 24 “LPC5411x USARTs”, Chapter 25 “LPC5411x Serial Peripheral Interfaces (SPI)”, and Chapter 27 “LPC5411x I2S interface”...
Page 5 UM10914 NXP Semiconductors LPC5411x User manual Revision history …continued Date Description • 20170308 In the Syscon chapter: – The code listing related to the PLL SELP, SELI, and SELR values has been updated, and all PLL code snippets have been moved to a common location.
Page 6 UM10914 NXP Semiconductors Chapter : Revision history …continued Date Description • 20160915 In the Syscon chapter, many changes are made regarding PDRUNCFG, Flash timing, and STARTER register details. • In the Power management chapter, various clarifications are made to details of reduced power modes.
Page 7 UM10914 NXP Semiconductors Chapter : Revision history …continued Date Description • 20160525 An incorrect mention of an SPI Flash Interface has been removed from the introduction. • In the Syscon chapter, block diagrams have been added for the Flash Accelerator and the frequency measurement functions.
Page 8 UM10914 Chapter 1: LPC5411x Introductory information Rev. 2.0 — 9 May 2018 User manual 1.1 Introduction The LPC5411x are Arm ® Cortex ® -M4 based microcontrollers for embedded applications. These devices include an optional Arm ® Cortex ® -M0+ coprocessor, up to 192 KB of on-chip SRAM, up to 256 KB on-chip flash, Full Speed USB device interface, a DMIC subsystem with dual-channel PDM microphone interface and I2S, five general-purpose timers, one versatile timer with PWM and many other capabilities (SCTimer/PWM), one...
Page 9 UM10914 NXP Semiconductors Chapter 1: LPC5411x Introductory information – Single cycle multiplier. – Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). – Non-maskable Interrupt (NMI) with a selection of sources. – Serial Wire Debug (SWD) with 4 breakpoints and 2 watchpoints.
Page 10 UM10914 NXP Semiconductors Chapter 1: LPC5411x Introductory information – 12-bit ADC with 12 input channels and with multiple internal and external trigger inputs and sample rates of up to 5.0 Msps. The ADC supports two independent conversion sequences. – Integrated temperature sensor connected to the ADC.
Page 11 UM10914 NXP Semiconductors Chapter 1: LPC5411x Introductory information – Wake-up from sleep, deep-sleep and deep power-down modes from the RTC alarm. – The Micro-tick Timer can wake-up the device from most reduced power modes by using the watchdog oscillator when no other on-chip resources are running, for ultra-low power wake-up.
Page 12 UM10914 NXP Semiconductors Chapter 1: LPC5411x Introductory information 1.3 Block diagram Notes: Each Flexcomm Interface includes USART, SPI, and I2C functions. Flexcomm Interfaces 6 and 7 each also provide an I2S function. Grey-shaded blocks indicate peripherals that provide DMA requests or are otherwise able to trigger DMA transfers.
Page 13 UM10914 NXP Semiconductors Chapter 1: LPC5411x Introductory information 1.4 Architectural overview The Arm Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is dedicated for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.
Page 14 UM10914 Chapter 2: LPC5411x Memory map Rev. 2.0 — 9 May 2018 User manual 2.1 General description The LPC5411x incorporates several distinct memory regions. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. The APB peripheral area (detailed in Figure 3) is divided into fixed 4 KB slots to simplify...
Page 15 UM10914 NXP Semiconductors Chapter 2: LPC5411x Memory map while the CPU is reading data from a buffer on a different AHB matrix port, there is no stall for either the CPU or the DMA. Sequences of data from the same peripheral could be alternated between RAM on each port.
Page 16 UM10914 NXP Semiconductors Chapter 2: LPC5411x Memory map 2.1.2 Memory mapping The overall memory map is shown in Figure 2 “Main memory map”. Details of APB peripheral mapping are shown in Figure 3 “APB memory map”. 1) The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.
Page 17 UM10914 NXP Semiconductors Chapter 2: LPC5411x Memory map Fig 3. APB memory map 2.1.3 AHB multilayer matrix The LPC5411x uses a multi-layer AHB matrix to connect the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters.
Page 18 UM10914 Chapter 3: LPC5411x Boot process Rev. 2.0 — 9 May 2018 User manual 3.1 Features • On-chip boot ROM. • Contains the boot loader with In-System Programming (ISP) facility and the following APIs: – In-Application Programming (IAP) of flash memory. –...
Page 19 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process • PIO0_12 for SPI MOSI (master out, slave in) data signal • PIO0_13 for SPI MISO (master in, slave out) data signal • PIO0_14 for SPI SSEL (select) signal • PIO0_4 for I2C/SPI IRQ pin to and from the host system 3.3 General description...
Page 20 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process 3.4 Boot process The following figures show the ROM's boot flow process of the LPC5411x. This includes ISP selection, CRP checks, and image type detection. (DE0 = Dual Enhanced image at sector 0, DEn- Dual Enhanced image at sector n (where n > 0), SE = Single Enhanced image).
Page 21 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process Fig 5. Simplified boot flow, figure 2 Fig 6. Simplified boot flow, figure 3 UM10914 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Page 22 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process 3.5 Image boot support The LPC5411x supports booting executable images from internal flash located at sector 0, but also supports enhanced images that can boot from sectors greater than 0, even if sector 0 is blank.
Page 23 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process For Dual Enhanced images not at sector 0, the image must be linked to run at the sector start address where the image is programmed and must be aligned on a sector boundary.
Page 24 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process 3.5.6 Modifications to startup code to enable enhanced boot support Several modifications need to be made to the startup code to enable enhanced boot support. The value at offset 0x24 in the image must contain an enhanced image marker and the value at offset 0x28 must point to a valid image header in the image.
Page 25 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process Table 4. Image Header structure Field Offset Size (bytes) Value Description header_marker 0x00 0xFEEDA5A5 Image header marker must always be 0xFEEDA5A5 img_type 0x04 Image type. 0 - IMG_NORMAL 1 - IMG_NO_CRC (All other values invalid, will not boot)
Page 26 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process CRC generation approach for an enhanced image and CRC parameters The following basic approach is used to generate the CRC length and value field on an enhanced image. 1. Determine the OFFSET in the image the CRC length and value fields are located.
Page 27 UM10914 NXP Semiconductors Chapter 3: LPC5411x Boot process 3.5.7.3 Dual enhanced Image Versioning The “Version” field in the image header is only used for Dual Enhanced image checks when 2 Dual Enhanced images are detected in sector 0 and another sector. The LPC5411x will boot the image with the higher version number.
Page 28 UM10914 Chapter 4: LPC5411x ISP and IAP Rev. 2.0 — 9 May 2018 User manual 4.1 How to read this chapter All LPC5411x devices include ROM-based services for programming and reading the flash memory in addition to other functions. In-System Programming works on an unprogrammed or previously programmed device using one from a selection of hardware interfaces.
Page 29 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP The operation of ECC is transparent to the running application. The ECC content itself is stored in a flash memory not accessible by user’s code to either read from it or write into it on its own.
Page 30 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.3.6 Code Read Protection (CRP) Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted.
Page 31 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.3.6.1 ISP entry protection In addition to the three CRP modes, the user can prevent the sampling of the pin for entering ISP mode and thereby release the pin for other applications. This is called the NO_ISP mode.
Page 32 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.4 USART ISP communication protocol All USART ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR>...
Page 33 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.5 USART ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
Page 34 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 8. ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 (no entry in ISP mode allowed) Erase page(s) yes; page 0 can only be erased when all yes;...
Page 35 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.5.3 Echo Table 11. USART ISP Echo command Command Input Setting: ON = 1 | OFF = 0 Return Code CMD_SUCCESS | PARAM_ERROR Description The default setting for echo command is ON. When ON the ISP command handler sends the received serial data back to the host.
Page 36 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.5.6 Prepare sectors for write operation This command makes flash write/erase operation a two-step process. Table 14. USART ISP Prepare sectors for write operation command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number.
Page 37 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 15. USART ISP Copy command Command Input Flash Address(DST): Destination flash address where data bytes are to be written. The destination address should be a 256 byte boundary. RAM Address(SRC): Source on-chip RAM address from where data bytes are to be read.
Page 38 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.5.9 Erase sectors Table 17. USART ISP Erase sector command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number. Return Code CMD_SUCCESS |...
Page 39 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.5.12 Read Part Identification number Table 20. USART ISP Read Part Identification command Command Input None. Return Code CMD_SUCCESS followed by part identification number (see Table 21). Description This command is used to read the part identification number.
Page 40 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.5.15 ReadUID Table 24. USART ReadUID command Command Input None Return Code CMD_SUCCESS followed by four 32-bit words of a unique serial number in ASCII format. The word sent at the lowest address is sent first.
Page 41 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 26. USART ISP Read flash signature command Command Input none Return Code CMD_SUCCESS followed by data in decimal format | CODE_READ_PROTECTION_ENABLED Description This command is used to read the signature of the entire flash memory. This command is blocked when code read protection is enabled.
Page 42 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.5.18 UART ISP Error codes Table 27. USART ISP Error codes Return Error code Description Code ERR_ISP_CMD_SUCCESS Command is executed successfully. Sent by ISP handler only when command given by the host has been completely and successfully executed.
Page 43 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP typedef enum ERR_ISP_BASE = 0x00000000, /*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1, /*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED, /*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED, /*0x00000006*/ ERR_ISP_COUNT_ERROR, /*0x00000007*/ ERR_ISP_INVALID_SECTOR, /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK, /*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, /*0x0000000A*/ ERR_ISP_COMPARE_ERROR, /*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */...
Page 44 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.6 IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. The result of the IAP command is returned in the result table pointed to by register r1. The user can reuse the command table for result by passing the same pointer in registers r0 and r1.
Page 45 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP respectively. Additional parameters are returned indirectly via memory. Some of the IAP calls require more than 4 parameters. If the Arm suggested scheme is used for the parameter passing/returning then it might create problems due to difference in the C compiler implementation from different vendors.
Page 46 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.6.1 Prepare sector(s) for write operation This command makes flash write/erase operation a two step process. Table 29. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation...
Page 47 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.6.3 Erase Sector(s) Table 31. IAP Erase Sector(s) command Command Erase Sector(s) Input Command code: 52 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
Page 48 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.6.6 Read Boot code version number Table 34. IAP Read Boot Code version number command Command Read boot code version number Input Command code: 55 (decimal) Parameters: None Status code CMD_SUCCESS Result Result0: 2 bytes of boot code version number.
Page 49 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.6.9 ReadUID Table 37. IAP ReadUID command Command Compare Input Command code: 58 (decimal) Status code CMD_SUCCESS Result Result0: The first 32-bit word (at the lowest address). Result1: The second 32-bit word.
Page 50 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.6.12 IAP Status Codes Table 40. IAP Status codes Summary Status Mnemonic Description code CMD_SUCCESS Command is executed successfully. INVALID_COMMAND Invalid command. SRC_ADDR_ERROR Source address is not on a word boundary.
Page 51 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.7 I2C and SPI ISP commands The LPC5411x I2C/SPI ISP allows programming and reprogramming internal flash via a set of commands on the I2C slave or SPI slave buses of the LPC5411x. These need to be connected to a host system that provides the I2C or SPI master connections to the LPC5411x.
Page 52 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.7.3 I2C/SPI ISP mode transaction protocol This section explains the high-level protocol used with the I2C and SPI interfaces. A typical transaction starts with the host sending a command packet, the LPC5411x processing the command packet, the LPC5411x optionally asserting the ISP1_IRQ line low when processing is complete, and then the host system getting the response packet.
Page 53 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Although SPI is bi-directional, the command and response packet phases only send data one way for each phase. During the command packet phase, a single SPI transfer occurs where the command and data is sent from the host system. In this phase, SSEL is asserted low, the command packet is sent, and then SSEL is deasserted.
Page 54 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.8 I2C/SPI ISP mode commands, data, and responses All of the supported commands, associated structures and data formats for those commands, and responses are explained in this section. Table 42. I2C/SPI ISP command summary...
Page 55 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.8.3 SH_CMD_BOOT (0xA3) command This command can be used to boot the application currently programmed into flash. This command only has a response if it cannot boot the application due to CRP level.
Page 56 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP The probe command is optional when the I2C or SPI ISP mode is re-invoked from an application using the ‘Re-invoke ISP’ IAP command. Only the interface selected with the ‘Re-invoke ISP’ IAP command will be active for the optional probe command.
Page 57 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 53. Response packet (error) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xA6 Processed command identifier length 0x00 On error this field is set to 4.
Page 58 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 58. Response packet (success) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xA8 Processed command identifier length 0x00 On Success this field is set to 0.
Page 59 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 63. Command packet Field Offset Size (bytes) Value Description command 0x0 0xAA ‘Page write’ command identifier crcCheck 0 – Do CRC check for this packet. 1 - Ignore CRC field for this packet.
Page 60 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 68. Response packet (error) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xAB Processed command identifier length On error this field is set to 4. errorCode Error code Error code specified in error.h parameters...
Page 61 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.8.13 SH_CMD_ READ_SUBBLOCK (0xAD) command The read sub-block command is used for reading partial data from a full flash block write. It is used when the host system cannot receive the entire data block to the LPC5411x in a single I2C transfer using the ‘Read block’...
Page 62 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 76. Response packet (success) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xAE Processed command identifier length 0x00 On Success this field is set to 0.
Page 63 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP Table 78. USART ISP Error codes Return Error code Description Code 0x13 ERR_ISP_CODE_READ_ Code read protection enabled. PROTECTION_ENABLED 0x14 Reserved. 0x15 Reserved. 0x16 Reserved. 0x17 ERR_ISP_FRO_NO_POWER FRO not turned on in the PDRUNCFG register.
Page 64 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP /** Structure describing Read/Write page command packet format. */ typedef struct { uint8_t cmd; /*!< Command ID */ uint8_t crc_check; /*!< specifies if we need to do CRC check before processing */ uint16_t page_nr;...
Page 65 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP /*0x00000006*/ ERR_ISP_COUNT_ERROR, /*0x00000007*/ ERR_ISP_INVALID_SECTOR, /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK, /*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, /*0x0000000A*/ ERR_ISP_COMPARE_ERROR, /*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */ /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */ /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */...
Page 66 UM10914 NXP Semiconductors Chapter 4: LPC5411x ISP and IAP 4.9 USB communication protocol In USB ISP MSC mode, the LPC5411x is enumerated as a Mass Storage Class (MSC) device to a PC or another embedded system. The MSC device presents an easy integration with the PC’s operating system.
Page 67 UM10914 Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) Rev. 2.0 — 9 May 2018 User manual 5.1 How to read this chapter Available interrupt sources may vary with specific LPC5411x device type. 5.2 Features • Nested Vectored Interrupt Controller that is an integral part of each CPU. •...
Page 68 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) Table 79. Connection of interrupt sources to the NVIC Interrupt Name Interrupt description Flags WDT, BOD Windowed watchdog timer, Brownout detect WARNINT - watchdog warning interrupt BODINTVAL - BOD interrupt level...
Page 69 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) 5.4 Register description The NVIC registers are located on the Arm private peripheral bus. Table 80. Register overview: NVIC (base address 0xE000 E000) Name Access Offset Description Reset Section...
Page 70 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) 5.4.1 Interrupt register bits and fields summary Table 81 shows the bits or fields in the NVIC that are relevant to each interrupt. Table 81. Registers related to each Interrupt source...
Page 71 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) 5.4.2 Interrupt Set-Enable Register 0 register The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are enabled via the ISER1...
Page 72 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) 5.4.3 Interrupt Set-Enable Register 1 register The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ICER0 and ICER1 registers (Section 5.4.4...
Page 73 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) Table 86. Interrupt Set-Pending Register 0 register Name Function 31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER0 registers (Table 82). Unused bits are reserved. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Page 74 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) 5.4.10 Interrupt Active Bit Register 0 The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. Bits in IABR are set while the corresponding interrupt service routines are in progress.
Page 75 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) Table 93. Interrupt Priority Register 1 Name Function Unused IP_PINT0 Pin interrupt / pattern match engine slice 0 priority. 0 = highest priority, 7 = lowest priority. 12:8 Unused 15:13 IP_PINT1 Pin interrupt / pattern match engine slice 1 priority.
Page 76 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) 5.4.16 Interrupt Priority Register 4 The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each interrupt can have one of 8 priorities for the Cortex-M4, 4 for the Cortex-M0+. 0 is the highest priority.
Page 77 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) Table 98. Interrupt Priority Register 6 …continued Name Function 23:21 IP_HWVAD Hardware Voice Activity Detect interrupt priority. 0 = highest priority, 7 = lowest priority. 28:24 - Unused 31:29 IP_USBACT USB Activity interrupt priority.
Page 78 UM10914 NXP Semiconductors Chapter 5: LPC5411x Nested Vectored Interrupt Controller (NVIC) Table 101. Interrupt Priority Register 9 Name Function Unused IP_CTIMER2 Standard counter/timer CTIMER2 interrupt priority. 0 = highest priority, 7 = lowest priority. 12:8 Unused 15:13 IP_CTIMER4 Standard counter/timer CTIMER4 interrupt priority. 0 = highest priority, 7 = lowest priority.
Page 79 FRO 12 MHz clock and the FRO 96 or 48 MHz clock (fro_hf) is not appropriate, use the PLL to boost the input frequency. The PLL can be set up by calling an API supplied by NXP Semiconductors. Also see Section 6.6.5 “System PLL functional...
Page 80 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) – CLKIN. – Watchdog oscillator. – The output of the system PLL. – The RTC 32 kHz oscillator. Section 6.5.22 “Main clock source select register A” Section 6.5.23 “Main clock source select register B”.
Page 81 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.4 General description 6.4.1 Clock generation The system control block facilitates the clock generation. Many clocking variations are possible. Figure 9 gives an overview of potential clock options. Table 104 describes signals on the clocking diagram.
Page 82 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Fig 9. Clock generation UM10914 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. User manual Rev. 2.0 — 9 May 2018...
Page 83 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5 Register description All system control block registers reside on word address boundaries. Details of the registers appear in the description of each function. System configuration functions are divided into 3 groups: •...
Page 84 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 105. Register overview: Main system configuration (base address 0x4000 0000) …continued Name Access Offset Description Reset value Section FCLKSEL1 0x2B4 Flexcomm Interface 1 clock source select 6.5.28 FCLKSEL2 0x2B8 Flexcomm Interface 2 clock source select 6.5.28...
Page 85 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 105. Register overview: Main system configuration (base address 0x4000 0000) …continued Name Access Offset Description Reset value Section STARTERCLR0 0x6C0 Clear bits in STARTER0 6.5.58 STARTERCLR1 0x6C4 Clear bits in STARTER1 6.5.59...
Page 86 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 108. AHB matrix priority register 0 (AHBMATPRIO, main syscon: offset 0x010) bit description Symbol Master Description Reset number value PRI_ICODE Cortex-M4 I-Code bus priority. Should typically be lower than PRI_DCODE for best operation.
Page 87 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Remark: If the NMISRC register is used to select an interrupt as the source of Non-Maskable interrupts, and the selected interrupt is enabled, one interrupt request can result in both a Non-Maskable and a normal interrupt. This can be avoided by disabling the normal interrupt in the NVIC.
Page 88 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 115. Reset captured PIO status register 1 (PIORESCAP1, main syscon: offset 0x0D4) bit description Symbol Description Reset value 31:0 PIORESCAP State of PIO1_31 through PIO1_0 for resets other than POR.
Page 89 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.10 Peripheral reset control register 1 The PRESETCTRL1 register allows software to reset specific peripherals. Writing a zero to any assigned bit in this register clears the reset and allows the specified peripheral to operate.
Page 90 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.11 Peripheral reset control set register 0 Writing a 1 to a bit position in PRESETCTRLSET0 sets the corresponding position in PRESETCTRL0. This is a write-only register. For bit assignments, see Table 116.
Page 91 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.15 System reset status register The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register.
Page 92 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.16 AHB Clock Control register 0 The AHBCLKCTRL0 register enables the clocks to individual system and peripheral blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the CPU, the SYSCON block, and the PMU.
Page 93 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.17 AHB Clock Control register 1 The AHBCLKCTRL1 register enables the clocks to individual peripheral blocks. Table 124. AHB Clock Control register 1 (AHBCLKCTRL1, main syscon: offset 0x204) bit description Symbol...
Page 94 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 126. Clock control set register 1 (AHBCLKCTRLSET1, main syscon: offset 0x224) bit description Symbol Description Reset value 31:0 CLK_SET1 Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL1 register, if they are implemented.
Page 95 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 129. Main clock source select register A (MAINCLKSELA, main syscon: offset 0x280) bit description Symbol Value Description Reset value Clock source for main clock source selector A FRO 12 MHz (fro_12m)
Page 96 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.24 CLKOUT clock source select register A This register pre-selects one of the internal oscillators for the clock sources visible on the CLKOUT pin. Table 131. CLKOUT clock source select register (CLKOUTSELA, main syscon: offset 0x288) bit description...
Page 97 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.27 USB clock source select register This register selects a clock source for the USB device. Table 134. USB clock source select register (USBCLKSEL, main syscon: offset 0x2A8) bit description Symbol...
Page 98 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.30 FRG clock source select register This register selects a clock source for the Fractional Rate Generator. Table 137. FRG clock source select register (FRGCLKSEL, main syscon: offset 0x2E8) bit description...
Page 99 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 140. Trace clock divider (TRACECLKDIV, main syscon: offset 0x304) bit description Symbol Description Reset value Clock divider value. 0: Divide by 1. … 255: Divide by 256. 31:8 Reserved. Read value is undefined, only zero should be written.
Page 100 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 144. USB clock divider register (USBCLKDIV, main syscon: offset 0x398) bit description Symbol Description Reset value Clock divider value. 0: Divide by 1. … 255: Divide by 256. 31:8 Reserved. Read value is undefined, only zero should be written.
Page 101 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.40 MCLK clock divider register This register determines the divider value for the MCLK output, if used by the application. Table 147. MCLK clock divider register (MCLKDIV, main syscon: offset 0x3AC) bit description...
Page 102 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.41 Flash configuration register Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG register. It is recommended to use the power mode entry API (see Chapter 8 “LPC5411x Power profiles/Power control...
Page 103 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 148. Flash configuration register (FLASHCFG, main syscon: offset 0x400) bit description Symbol Value Description Reset value PREFOVR Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched.
Page 104 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.44 Frequency measure function control register This register starts the frequency measurement function and stores the result in the CAPVAL field. The target frequency can be calculated as follows with the frequencies...
Page 105 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 3. Set bit 30 (HSPDCLK) in FROCTRL register to 1. 4. Switch the main clock to fro_hf clock. Table 153. FRO control register (FROCTRL, main syscon: offset 0x500) bit description Symbol...
Page 106 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.47 Watchdog oscillator control register This register controls the frequency of the watchdog oscillator, in the range of 6 kHz to 1.5 MHz. This oscillator is connected to the watchdog timer and the Micro-tick Timer. The low-power nature of this oscillator limits its accuracy to +/- 40% over temperature, voltage, and silicon processing variations.
Page 107 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.48 RTC oscillator control register This register enables the 32 kHz output of the RTC oscillator (32k_clk). This clock can be used to create the main clock when the PLL input or output is selected as the clock source to the main clock.
Page 108 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.49 PLL registers The PLL provides a wide range of frequencies and can potentially be used for many on-chip functions. the PLL can be used with or without a spread spectrum clock generator.
Page 109 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.49.2 System PLL status register The read-only SYSPLLSTAT register provides the PLL lock status Remark: The lock status does not reliably indicate the PLL status for the following two configurations: spread-spectrum mode or fractional enabled or low input clock frequencies such as 32 kHz.
Page 110 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.49.5 Spread spectrum control with the System PLL The spread spectrum functionality can be used to modulate the PLL output frequency. This can decrease electromagnetic interference (EMI) in an application. The Spread Spectrum Clock Generator can be used in several ways: •...
Page 111 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 161. System PLL spread spectrum control register 1 (SYSPLLSSCTRL1, main syscon: offset 0x594) bit description Symbol Value Description Reset value 18:0 M- divider value with fraction. MD[18:11]: integer portion of the feedback divider value.
Page 112 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.49.6 Calculating NDEC, MDEC, PDEC, SELP, SELI, and SELR values NDEC, MDEC, and PDEC do not use the direct binary representations of the desired settings directly. Instead, an encoded version of the values is used. SELP, SELI, and SELR values are determined by the MDEC.
Page 113 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) default: for (i = P; i <= P_max; i++) x = (((x ^ (x>>2)) & 1) << 4) | ((x>>1) & 0xF); } PDEC[6:0] = x; Remark: While the PLL output is in use, do not change the PDEC value. Changing the PDEC value changes the PLL output frequency and can cause the system to fail.
Page 114 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.50 Sleep configuration register 0 The PDSLEEPCFG0 register controls the power to various analog blocks while the CPU is in the deep sleep reduced power mode. Entering reduced power modes is typically accomplished by calling the power mode entry API.
Page 115 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 163. Power Configuration register (PDRUNCFG0, main syscon: offset 0x610) bit description Symbol Description Reset value PDEN_SYS_PLL System PLL. 0 = Powered; 1 = Powered down. PDEN_VREFP Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19.
Page 116 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 166. Start enable register 0 (STARTER0, main syscon: offset 0x680) bit description Symbol Description Reset value WDT, BOD WWDT and BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
Page 117 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 167. Start enable register 1 (STARTER1, main syscon: offset 0x684) bit description Symbol Description Reset value PINT4 GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
Page 118 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Table 171. Start enable clear register 1 (STARTERCLR1, main syscon: offset 0x6C4) bit description Symbol Description Reset value 31:0 START_CLR1 Writing ones to this register clears the corresponding bit or bits in the STARTER1 register, if they are implemented.
Page 119 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.61 Dual-CPU related registers These registers control usage aspects of the two CPUs in selected devices. They are not used in other devices that only provide a single CPU. 6.5.61.1 CPU Control register The CPUCTRL register provides control for the 2 CPUs.
Page 120 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.61.2 Coprocessor Boot register CPBOOT can be used in an application that uses both CPUs in order to send the slave processor (the CPU not selected as the master by the MASTERCPU bit in the CPUCTRL register) to an appropriate boot address that is different than the master CPU.
Page 121 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.63 JTAG ID code register This register contains the JTAG ID code. Table 178. JTAG ID code register (JTAGIDCODE, main syscon: offset 0xFF4) bit description Symbol Description Value 31:0 JTAGID JTAG ID code.
Page 122 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.66 Asynchronous peripheral reset control register The ASYNCPRESETCTRL register allows software to reset specific peripherals attached to the async APB bridge. Writing a zero to any assigned bit in this register clears the reset and allows the specified peripheral to operate.
Page 123 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.5.69 Asynchronous APB clock control register This register controls how the clock selected for the asynchronous APB peripherals is divided to provide the clock to the asynchronous peripherals. The clock will be stopped if the DIV field is set to zero.
Page 124 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Remark: This selection is internally synchronized: the clock being switched from and the clock being switched to must both be running and have occurred in specific states before the selection actually changes.
Page 125 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.6 Functional description 6.6.1 Reset Reset has the following sources: • The RESET pin. • Watchdog reset. • Power-On Reset (POR). • Brown Out Detect (BOD). • Arm software reset. •...
Page 126 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) If the BOD reset is enabled, the forced BOD reset can wake up the chip from reduced power modes, not including deep power-down. 6.6.4 Flash accelerator functional description The flash accelerator block allows maximization of the performance of the CPU when it is running code from flash memory, while also saving power.
Page 127 MHz (e.g. the 12 MHz FRO) can be divided down to 1 MHz, then multiplied up to any other integer MHz (e.g. 13, 14, 15, etc.).The PLL can be set up by calling an API supplied by NXP Semiconductors. Also see Section 6.5.49 “PLL registers”, and...
Page 128 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) • Lock detector. • Power-down mode. • Fractional divider mode. • Spread Spectrum mode. 6.6.5.2 PLL description A number of sources may be used as an input to the PLL, see Figure 9.
Page 129 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.6.5.2.2 Power-down To reduce the power consumption when the PLL clock is not needed, a PLL power-down mode has been incorporated. This mode is enabled by setting the PDEN_SYS_PLL bit to...
Page 130 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Normal mode with optional pre-divide In the equations, use N = 1 when the pre-divider is not used: When the extra divide by 2 is in the feedback divider path (BYPASSCCODIV2 = 0):...
Page 131 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Fig 12. System PLL block diagram showing spread spectrum and fractional divide operation 6.6.5.3.3 Spread Spectrum mode The spread spectrum functionality can be used to modulate the PLL output frequency automatically, in a programmable manner. This can decrease electromagnetic interference (EMI) in an application.
Page 132 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) Triangular wave modulation: For the center spread triangular waveform modulation with a modulation frequency depth δfmodpk-pk and a modulation frequency fm, the clock cycle displacement and spectral tone reduction ΔP can be calculated. The theoretical maximum...
Page 133 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.6.5.3.4 PLL power-down mode If the PLL is not used, or if it there are cases where it is turned off in a running application, power can be saved by putting the PLL in power-down mode. Before this is done, the CPU and any peripherals that are not meant to stopped as well must be running from some other clock source.
Page 134 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) – Fcco is in the range of 75 MHz to 150 MHz. – Fout is in the range of 1.2 MHz to 150 MHz. – The pre-divider is either bypassed, or N is in the range of 2 to 256.
Page 135 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 11. Connect the PLL to whichever downstream function(s) it will be clocking. The of the clocking structure may be seen in Figure 9 “Clock generation”. 6.6.6 Frequency measure function The Frequency Measure circuit is based on two 14-bit counters, one clocked by the reference clock and one by the target clock.
Page 136 UM10914 NXP Semiconductors Chapter 6: LPC5411x System configuration (SYSCON) 6.6.6.1 Accuracy The frequency measurement function can measure the frequency of any on-chip (or off-chip) clock (referred to as the target clock) to a high degree of accuracy using another on-chip clock of known frequency as a reference.
Page 137 UM10914 Chapter 7: LPC5411x Power management Rev. 2.0 — 9 May 2018 User manual 7.1 Introduction This chapter provides an overview of power related information about LPC5411x devices. These devices include a variety of power switches and clock switches to allow fine tuning power usage to match requirements at different performance levels and reduced power modes.
Page 138 UM10914 NXP Semiconductors Chapter 7: LPC5411x Power management Through the power profiles API, selected peripherals such as USB, DMIC, SPI, I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left running in deep sleep mode. 4. Deep power-down mode: Deep power-down mode shuts down virtually all on-chip power consumption, but requires a significantly longer wake-up time.
Page 139 UM10914 NXP Semiconductors Chapter 7: LPC5411x Power management Table 194. Wake-up sources for reduced power modes Power mode Wake-up source Conditions Deep-sleep Pin interrupts Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers. • BOD interrupt Enable interrupt in NVIC and STARTER0 registers.
Page 140 UM10914 NXP Semiconductors Chapter 7: LPC5411x Power management 7.3 Functional description 7.3.1 Power management The LPC5411x support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption.
Page 141 UM10914 NXP Semiconductors Chapter 7: LPC5411x Power management 7.3.3 Sleep mode In sleep mode, the system clock to the CPU is stopped and execution of instructions is suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be clocked in the AHBCLKCTRL registers, continue operation during sleep mode and may generate interrupts to cause the processor to resume execution.
Page 142 UM10914 NXP Semiconductors Chapter 7: LPC5411x Power management GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB, DMIC, SPI, I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left running in deep sleep mode The FRO, RTC oscillator, and the watchdog oscillator can be left running.
Page 143 UM10914 NXP Semiconductors Chapter 7: LPC5411x Power management • RTC alarm signal or wake-up signal. See Chapter 18. Interrupts must also be enabled in the STARTER1 register (Table 167) and in the NVIC. 7.3.5 Deep power-down mode In deep power-down mode, power and clocks are shut off to the entire chip with the exception of the RTC.
Page 144 UM10914 Chapter 8: LPC5411x Power profiles/Power control API Rev. 2.0 — 9 May 2018 User manual 8.1 How to read this chapter The Power profiles and Power control APIs can be implemented using the power library from LPCOpen software package, or the SDK software package available on nxp.com. 8.2 Features •...
Page 145 UM10914 NXP Semiconductors Chapter 8: LPC5411x Power profiles/Power control API Table 195. Power API calls (available in the LPCOpen software package) Function prototype API description Section Power API PLL configuration routine.This API sets up basic PLL operation. 8.4.1 uint32_t Chip_POWER_SetPLL (uint32_t multiply_by, uint32_t input_freq);...
Page 146 UM10914 NXP Semiconductors Chapter 8: LPC5411x Power profiles/Power control API 8.4.1.1 Param0: multiplier The input parameter multiplier (Param0) specifies the feedback multiplier for the PLL. The range supported is from 1 to 16. 8.4.1.2 Param1: input_freq The input frequency is the clock rate of the PLL input. The input frequency times the multiplier must not be greater than 100 MHz.
Page 147 UM10914 NXP Semiconductors Chapter 8: LPC5411x Power profiles/Power control API 8.4.3 Chip_POWER_EnterPowerMode (LPCOpen) and POWER_EnterPowerMode (SDK) The Chip_POWER_EnterPowerMode and POWER_EnterPowerMode APIs prepare the part, then enter any of the low power modes. Specifically for the deep-sleep mode, the API function configures which analog components remain running in those two modes, so that an interrupt from one of the analog peripherals can wake up the part.
Page 148 UM10914 NXP Semiconductors Chapter 8: LPC5411x Power profiles/Power control API 8.4.4 Chip_POWER_SetLowPowerVoltage This routine sets up internal voltage levels for low power regulation mode. The selected operating frequency must be either 12 MHz or 48 MHz, the two optimal frequencies for power dissipation for the device running from the FRO.
Page 149 UM10914 NXP Semiconductors Chapter 8: LPC5411x Power profiles/Power control API /* WDT_OSC and BOD are turned on */ POWER_DEEP_SLEEP, PDRUNCFG_PD_WDT_OSC | Chip_POWER_EnterPowerMode PDRUNCFG_PD_BOD_RESET | PDRUNCFG_PD_BOD_INTR); /* going to deep-sleep mode. */ UM10914 All information provided in this document is subject to legal disclaimers.
Page 150 UM10914 Chapter 9: LPC5411x I/O pin configuration (IOCON) Rev. 2.0 — 9 May 2018 User manual 9.1 How to read this chapter The IOCON block is included on all LPC5411x parts. Registers for pins that are not available on a specific package are reserved. Table 204.
Page 151 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) 9.4 General description 9.4.1 Pin configuration Fig 14. Pin configuration 9.4.2 IOCON registers The IOCON registers control the functions of device pins. Each GPIO pin has a dedicated control register to select its function and characteristics. Each pin has a unique set of functional capabilities.
Page 152 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) pins. If a peripheral input function is defined as coming from more than one source, the values will be logically combined, possibly resulting in incorrect peripheral operation. Therefore care should be taken to avoid this situation.
Page 153 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) 9.4.2.6 Input filter Some pins include a filter that can be selectively disabled by setting the FILTEROFF bit. The filter suppresses input pulses smaller than about 10 ns. 9.4.2.7 Output slew rate The SLEW bits of digital outputs that do not need to switch state very quickly should be set to “standard”.
Page 154 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) 9.5 Register description Each port pin PIOm_n has one IOCON register assigned to control the characteristics of the pin. Remark: See to the Pinning information section of the appropriate device data sheet for...
Page 155 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) Table 205. Register overview: I/O configuration (base address 0x4000 1000) Name Pin type Access Offset Description Reset value Section PIO1_3 0x08C Pin control for port 1 pin 3. Includes an ADC input.
Page 156 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) 9.5.1 Type D IOCON registers (PIO0) This IOCON register description applies to most port pins. Other pins include ADC or I2C functions that alter the contents of the related IOCON registers.
Page 157 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 207. Type D I/O Control registers: FUNC values and pin functions for port 0 Regname FUNC = 0 FUNC = 1 FUNC = 2...
Page 158 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 208. Type D I/O Control registers: FUNC values and pin functions for port 1 Regname FUNC = 0 FUNC = 1 FUNC = 2 FUNC = 3...
Page 159 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) 9.5.2 Type I IOCON registers (PIO0) This IOCON table applies to pins PIO0_23 to PIO0_26. See Table 210 for recommended setting for I2C operation. See Table 211 for function available on type I pins.
Page 160 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) Table 211. Type I I/O Control registers: FUNC values and pin functions Regname/FUNC = 0 FUNC = 1 FUNC = 2 FUNC = 3 FUNC = 4 FUNC = 5...
Page 161 UM10914 NXP Semiconductors Chapter 9: LPC5411x I/O pin configuration (IOCON) 9.5.3 Type A IOCON registers (PIO0, PIO1) This IOCON table applies to pins: • PIO0_29 to PIO0_31 • PIO1_0 to PIO1_8 Table 213 for function available on type I pins.
Page 162 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 213. Type A I/O Control registers: FUNC values and pin functions Reg name FUNC = 0 FUNC = 1 FUNC = 2 FUNC = 3...
Page 163 UM10914 Chapter 10: LPC5411x Input multiplexing (INPUT MUX) Rev. 2.0 — 9 May 2018 User manual 10.1 How to read this chapter Input multiplexing is present on all LPC5411x devices. Depending on the package, not all inputs from external pins may be available. 10.2 Features •...
Page 164 UM10914 NXP Semiconductors Chapter 10: LPC5411x Input multiplexing (INPUT MUX) 10.5.1 Pin interrupt input multiplexing The input mux for the pin interrupts and pattern match engine multiplexes all existing pins from ports 0 and 1. Fig 15. Pin interrupt multiplexing 10.5.2 DMA trigger input multiplexing...
Page 165 UM10914 NXP Semiconductors Chapter 10: LPC5411x Input multiplexing (INPUT MUX) 10.6 Register description All input mux registers reside on word address boundaries. Details of the registers appear in the description of each function. All address offsets not shown in Table 215 are reserved and should not be written to.
Page 166 UM10914 NXP Semiconductors Chapter 10: LPC5411x Input multiplexing (INPUT MUX) 10.6.1 Pin interrupt select registers Each of these 8 registers selects one pin from among ports 0 and 1 as the source of a pin interrupt or as the input to the pattern match engine. To select a pin for any of the 8 pin interrupts or pattern match engine inputs, write the GPIO port pin number as 0 to 31 for pins PIO0_0 to PIO0_31 to the INTPIN bits.
Page 167 UM10914 NXP Semiconductors Chapter 10: LPC5411x Input multiplexing (INPUT MUX) 10.6.2 DMA trigger input mux registers 0 to 19 With the DMA trigger input mux registers, one trigger input can be selected for each of the DMA channels from the potential internal sources. By default, none of the triggers are selected.
Page 168 UM10914 NXP Semiconductors Chapter 10: LPC5411x Input multiplexing (INPUT MUX) 10.6.4 Frequency measure function reference clock select register This register selects a clock for the reference clock of the frequency measure function. By default, no clock is selected. Also see: •...
Page 169 UM10914 NXP Semiconductors Chapter 10: LPC5411x Input multiplexing (INPUT MUX) Table 220. Frequency measure function target clock select register (FREQMEAS_TARGET, offset 0x184) bit description Symbol Description Reset value CLKIN Clock source number (decimal value) for frequency measure function target clock:...
Page 170 UM10914 Chapter 11: LPC5411x General Purpose I/O (GPIO) Rev. 2.0 — 9 May 2018 User manual 11.1 How to read this chapter GPIO registers support up to 32 pins on each port. Depending on the device and package type, a subset of those pins may be available, and the unused bits in GPIO registers are reserved (see Table 204).
Page 171 UM10914 NXP Semiconductors Chapter 11: LPC5411x General Purpose I/O (GPIO) 11.5 Register description Note: In all GPIO registers, bits that are not shown are reserved. GPIO port addresses can be read and written as bytes, halfwords, or words. Remark: A reset value noted as “ext” in this table and subsequent tables indicates that the data read after reset depends on the state of the pin, which in turn may depend on an external source.
Page 172 UM10914 NXP Semiconductors Chapter 11: LPC5411x General Purpose I/O (GPIO) 11.5.1 GPIO port byte pin registers Each GPIO pin has a byte register in this address range. Software typically reads and writes bytes to access individual pins, but can read or write halfwords to sense or set the state of two pins, and read or write words to sense or set the state of four pins.
Page 173 UM10914 NXP Semiconductors Chapter 11: LPC5411x General Purpose I/O (GPIO) Table 225. GPIO mask port register (MASK[0:1], offset [0x2080:0x2084]) bit description Symbol Description Reset value Access 31:0 MASKP Controls which bits corresponding to PIOm_n are active in the MPIN register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.).
Page 174 UM10914 NXP Semiconductors Chapter 11: LPC5411x General Purpose I/O (GPIO) 11.5.8 GPIO port clear registers Output bits can be cleared by writing ones to these write-only registers, regardless of MASK registers. Table 229. GPIO clear port register (CLR[0:1], offset [0x2280:0x2284]) bit description...
Page 175 UM10914 NXP Semiconductors Chapter 11: LPC5411x General Purpose I/O (GPIO) Table 233. GPIO port direction toggle register (DIRNOT[0:1], offset 0x2480:0x2484) bit description Symbol Description Reset value Access 31:0 DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.
Page 176 UM10914 NXP Semiconductors Chapter 11: LPC5411x General Purpose I/O (GPIO) 11.6 Functional description 11.6.1 Reading pin state Software can read the state of all GPIO pins except those selected for analog input or output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O Configuration”...
Page 177 UM10914 NXP Semiconductors Chapter 11: LPC5411x General Purpose I/O (GPIO) 11.6.3 Masked I/O A port’s MASK register defines which of its pins should be accessible in its MPIN register. Zeroszeros in MASK enable the corresponding pins to be read from and written to MPIN.
Page 178 UM10914 Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Rev. 2.0 — 9 May 2018 User manual 12.1 How to read this chapter The pin interrupt generator and the pattern match engine are available on all LPC5411x parts. 12.2 Features •...
Page 179 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) 12.3 Basic configuration • Pin interrupts: – Select up to eight external interrupt pins from all digital port pins on ports 0 and 1 in the Input Mux block (Table 216).
Page 180 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) 12.4 Pin description The inputs to the pin interrupt and pattern match engine are determined by the pin interrupt select registers in the Input mux. See Section 10.6.1 “Pin interrupt select registers”.
Page 181 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) • Edge with memory (sticky): A rising edge, a falling edge, or a rising or falling edge that is detected at any time after the edge-detection mechanism has been cleared. The input qualifies as detected (the detect logic output remains HIGH) until the pattern match engine detect logic is cleared again.
Page 182 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Figure 19 for the detect logic block. Fig 18. Pattern match engine connections The pattern match logic continuously monitors the eight inputs and generates interrupts when any one or more minterms (product terms) of the specified boolean expression is matched.
Page 183 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) minterm will be asserted whenever that minterm is matched. (See bit slice drawing Figure 19). The pattern match capability can be used to create complex software state machines.
Page 184 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) 12.6 Register description Table 234. Register overview: Pin interrupts/pattern match engine (base address 0x4000 4000) Name Access Offset Description Reset value Section Pin interrupt related registers: ISEL 0x000 Pin Interrupt Mode register 12.6.1...
Page 185 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) 12.6.1 Pin interrupt mode register For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 216), one bit in the ISEL register determines whether the interrupt is edge or level sensitive.
Page 186 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 238. Pin interrupt level or rising edge interrupt clear register (CIENR, offset 0x00C) bit description Symbol Description Reset value Access CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register.
Page 187 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) • If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is selected. Table 241. Pin interrupt active level or falling edge interrupt clear register (CIENF, offset 0x018) bit description...
Page 188 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) 12.6.10 Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones to this register clears both rising- and falling-edge detection for the pin.
Page 189 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 245. Pattern match interrupt control register (PMCTRL, offset 0x028) bit description Symbol Value Description Reset value ENA_RXEV Enables the RXEV output to the CPU when the specified boolean expression evaluates to true.
Page 190 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 246. Pattern match bit-slice source register (PMSRC, offset 0x02C) bit description Symbol Value Description Reset value 13:11 SRC1 Selects the input source for bit slice 1 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
Page 191 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 246. Pattern match bit-slice source register (PMSRC, offset 0x02C) bit description Symbol Value Description Reset value 25:23 SRC5 Selects the input source for bit slice 5 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
Page 192 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) • Non-sticky: Every time an edge (rising or falling) is detected, the detect logic output for this pin goes HIGH. This bit is cleared after one clock cycle, and the edge detect...
Page 193 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 247. Pattern match bit slice configuration register (PMCFG, offset 0x030) bit description …continued Symbol Value Description Reset value Reserved. Bit slice 7 is automatically considered a product end point.
Page 194 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 247. Pattern match bit slice configuration register (PMCFG, offset 0x030) bit description …continued Symbol Value Description Reset value 16:14 CFG2 Specifies the match contribution condition for bit slice 2.
Page 195 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 247. Pattern match bit slice configuration register (PMCFG, offset 0x030) bit description …continued Symbol Value Description Reset value 22:20 CFG4 Specifies the match contribution condition for bit slice 4.
Page 196 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Table 247. Pattern match bit slice configuration register (PMCFG, offset 0x030) bit description …continued Symbol Value Description Reset value 28:26 CFG6 Specifies the match contribution condition for bit slice 6.
Page 197 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) 12.7 Functional description 12.7.1 Pin interrupts In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits, corresponding to the pins called out by the PINTSEL0-7 registers.
Page 198 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) – SRC7: 111 - select input 7 for bit slice 7 • PMCFG register (Table 247): – PROD_ENDPTS0 = 1 – PROD_ENDPTS02 = 1 – PROD_ENDPTS5 = 1 –...
Page 199 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) 12.7.3 Pattern match engine edge detect examples Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the system clock for simplicity.
Page 200 UM10914 NXP Semiconductors Chapter 12: LPC5411x Pin interrupt and pattern match (PINT) Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the system clock for simplicity. Fig 22. Pattern match engine examples: Windowed non-sticky edge detect evaluates as false UM10914 All information provided in this document is subject to legal disclaimers.
Page 201 UM10914 Chapter 13: LPC5411x Group GPIO input interrupt (GINT0/1) Rev. 2.0 — 9 May 2018 User manual 13.1 Features • The inputs from any number of digital pins can be enabled to contribute to a combined group interrupt. • The polarity of each input enabled for the group interrupt can be configured HIGH or LOW.
Page 202 UM10914 NXP Semiconductors Chapter 13: LPC5411x Group GPIO input interrupt (GINT0/1) Fig 23. Group GPIO interrupt block diagram 13.4 Register description Note: In all registers, bits that are not shown are reserved. Table 249. Register overview: GROUP0 interrupt (base address 0x4000 2000 (GINT0) and 0x4000 3000 (GINT1))
Page 203 UM10914 NXP Semiconductors Chapter 13: LPC5411x Group GPIO input interrupt (GINT0/1) 13.4.2 GPIO grouped interrupt port polarity registers The grouped interrupt port polarity registers determine how the polarity of each enabled pin contributes to the grouped interrupt. Each port is associated with its own port polarity register, and the values of both registers together determine the grouped interrupt.
Page 204 UM10914 Chapter 14: LPC5411x DMA controller Rev. 2.0 — 9 May 2018 User manual 14.1 How to read this chapter The DMA controller is available on all LPC5411x devices. 14.2 Features • 20 channels, 19 of which are connected to peripheral DMA requests. These come from the Flexcomm Interface (USART, SPI, I C, and I S), and digital microphone.
Page 205 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.4 Pin description The DMA controller has no direct pin connections. However, some DMA triggers can be associated with pin functions (see Section 14.5.1.2). 14.5 General description Fig 24. DMA block diagram 14.5.1 DMA requests and triggers...
Page 206 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller request is likely to require transferring several non-contiguous result registers at once (see Chapter 29 “LPC5411x 12-bit ADC controller (ADC)”). It might also require other things to be done that can be done by the DMA without software intervention. This model fits better with the trigger facility, so that is how the ADC is connected to the DMA controller.
Page 207 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.5.1.1.1 DMA with I2C monitor mode The I C monitor function may be used with DMA if one of the channels related to the same Flexcomm Interface is available. Table 254. DMA with the I...
Page 208 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.5.1.3 Trigger operation detail A trigger of some kind is always needed to start a transfer on a DMA channel. This can be a hardware or software trigger, and can be used in several ways.
Page 209 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller When a DMA transfer involves a fixed peripheral data register, such as, when moving data from memory to a peripheral or moving data from a peripheral to memory, the address used for SRCINC or DSTINC (whichever corresponds to the fixed peripheral data address) is the address of the peripheral data register.
Page 210 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 258: Channel Descriptor for a single buffer Offset Description + 0x4 Source data end address + 0x8 Destination data end address + 0xC (not used) This case is identified by the Reload bit in the XFERCFG register = 0. When the DMA channel receives a DMA request or trigger (depending on how it is configured), it performs one or more transfers as configured, then stops.
Page 211 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller For example, if 4 data samples from several peripherals need to be interleaved into a single data structure, this may be done while the data is being read in by the DMA. Setting SRCINC to 4x width for each channel involved will allow room for 4 samples in a row in the buffer memory.
Page 212 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller To use channel chaining, first configure DMA channels x and y as if no channel chaining would be used. Then: • For channel x: – If channel x is configured to auto reload the descriptor on exhausting of the...
Page 213 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller These wake-ups are based on peripheral FIFO levels, not directly related to peripheral DMA requests and interrupts. See Section 6.5.60 for more information. UM10914 All information provided in this document is subject to legal disclaimers.
Page 214 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.6 Register description The DMA registers are grouped into DMA control, interrupt and status registers and DMA channel registers. DMA transfers are controlled by a set of three registers per channel, the CFG[0:19], CTRLSTAT[0:19], and XFERCFG[0:19] registers.
Page 215 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 260. Register overview: DMA controller (base address 0x4008 2000) Name Access Offset Description Reset value Section Channel 4 registers CFG4 0x440 Configuration register for DMA channel 4. 14.6.16 CTLSTAT4 0x444 Control and status register for DMA channel 4.
Page 216 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 260. Register overview: DMA controller (base address 0x4008 2000) Name Access Offset Description Reset value Section CFG14 0x4E0 Configuration register for DMA channel 14. 14.6.16 CTLSTAT14 0x4E4 Control and status register for DMA channel 14.
Page 217 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.6.1 Control register The CTRL register contains global the control bit for a enabling the DMA controller. Table 261. Control register (CTRL, offset 0x000) bit description Symbol Value Description Reset value ENABLE DMA controller master enable.
Page 218 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 264. Channel Descriptor map Descriptor Table offset Channel Descriptor for DMA channel 0 0x000 Channel Descriptor for DMA channel 1 0x010 Channel Descriptor for DMA channel 2 0x020 Channel Descriptor for DMA channel 3...
Page 219 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 266. Enable Clear register 0 (ENABLECLR0, offset 0x028) bit description Symbol Description Reset value 31:0 CLR Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.
Page 220 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 269. Error Interrupt register 0 (ERRINT0, offset 0x040) bit description Symbol Description Reset value 31:0 ERR Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device.
Page 221 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.6.12 Interrupt B register The INTB0 register contains the interrupt B status for each DMA channel. The status will be set when the SETINTB bit is 1 in the transfer configuration for a channel, when the descriptor becomes exhausted.
Page 222 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.6.15 Abort register The Abort0 register allows aborting operation of a DMA channel if needed. To abort a selected channel, the channel should first be disabled by clearing the corresponding Enable bit by writing a 1 to the proper bit ENABLECLR. Then wait until the channel is no longer busy by checking the corresponding bit in BUSY.
Page 223 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.6.16 Channel configuration registers The CFGn register contains various configuration options for DMA channel n. Table 278 for a summary of trigger options. Table 277. Configuration registers for channel 0 to 19 (CFG[0:19], offset 0x400 (CFG0) to offset 0x530 (CFG19)) bit...
Page 224 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 277. Configuration registers for channel 0 to 19 (CFG[0:19], offset 0x400 (CFG0) to offset 0x530 (CFG19)) bit description Symbol Value Description Reset value 11:8 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
Page 225 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 278. Trigger setting summary TrigBurst TrigType TrigPol Description Hardware DMA trigger is high level sensitive. The BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap. Hardware DMA trigger is falling edge sensitive. The BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap, and also determines how much data is transferred for each trigger.
Page 226 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller 14.6.18 Channel transfer configuration registers The XFERCFGn register contains transfer related configuration information for DMA channel n. Using the Reload bit, this register can optionally be automatically reloaded when the current settings are exhausted (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed.
Page 227 UM10914 NXP Semiconductors Chapter 14: LPC5411x DMA controller Table 280. Transfer configuration registers for channel 0 to 19 (XFERCFG[0:19], offset 0x408 (XFERCFG0) to offset 0x538 (XFERCFG19)) bit description Symbol Value Description Reset value WIDTH Transfer width used for this DMA channel.
Page 228 UM10914 Chapter 15: LPC5411x SCTimer/PWM (SCT) Rev. 2.0 — 9 May 2018 User manual 15.1 How to read this chapter The SCTimer/PWM is available on all LPC5411x devices. Remark: For a detailed description of SCTimer/PWM applications and code examples, Ref. 3 “AN11538”.
Page 229 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) – Match register 0 can be used as an automatic limit. – In bi-directional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs.
Page 230 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Fig 27. SCT connections 15.4 Pin description Chapter 9 to assign the SCT functions to external pins. SCT input signals are predefined. The signals from external pins and internal signals are connected directly to the SCT inputs and not routed through IOCON.
Page 231 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 283: Suggested SCT input pin settings IOCON bit(s) Type D pin I2CFILTER: Set to 1 I2CDRIVE: Set to 0. FILTEROFF: Generally set to 1. DIGIMODE: Set to 1. INVERT: Set to 0.
Page 232 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) • Set, clear, or toggle any SCT output. • Force a capture of the count value into any capture registers. • Generate an interrupt of DMA request. The SCT allows the user to group and filter events, thereby selecting some events to be enabled together while others are disabled in a given context.
Page 233 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Fig 28. SCTimer/PWM block diagram Fig 29. SCTimer/PWM counter and select logic Remark: In this chapter, the term bus error indicates an SCT response that makes the processor take an exception. UM10914 All information provided in this document is subject to legal disclaimers.
Page 234 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.6 Register description The register addresses of the SCTimer/PWM are shown in Table 285. For most of the SCT registers, the register function depends on the setting of certain other register bits: 1.
Page 235 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 285. Register overview: SCTimer/PWM (base address 0x4008 5000) …continued Name Access Offset Description Reset value Section REGMODE_L 0x04C SCT match/capture mode register low counter 16-bit 15.6.11 REGMODE_H 0x04E SCT match/capture registers mode register high counter 15.6.11...
Page 236 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 285. Register overview: SCTimer/PWM (base address 0x4008 5000) …continued Name Access Offset Description Reset value Section EV4_STATE 0x320 SCT event state register 4 15.6.24 EV4_CTRL 0x324 SCT event control register4 15.6.25...
Page 237 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) select one event m MATCH MATCHSEL MATCH[i:0] COMBMODE change state select one STATELD/ IOSEL EVm_CTRL STATEV in bidirectional mode, inputs select counter direction DIRECTION SCT_IN[q:0] outputs select in which states the event is allowed...
Page 238 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.6.1.1 Counter configuration and control registers The SCT contains two registers for configuring the SCT and monitor and control its operation by software. • The configuration register (CONFIG) configures the SCT in single, 32-bit counter mode or in dual, 16-bit counter mode, configures the clocking and clock synchronization, and configures automatic limits and the use of reload registers.
Page 239 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.6.1.5 Event select registers for setting or clearing the outputs This group contains the registers that select the events which affect the level of each SCT output. Also included are registers to manage conflicts that occur when events try to set or clear the same output.
Page 240 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.6.2 SCT configuration register This register configures the overall operation of the SCT. Write to this register before any other registers. Only word-writes are permitted to this register. Attempting to write a half-word value results in a bus error.
Page 241 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 286. SCT configuration register (CONFIG, offset 0x000) bit description …continued Symbol Value Description Reset value NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers.
Page 242 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) If bit UNIFY = 0 in the CONFIG register, this register can be written to as two registers CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation.
Page 243 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 287. SCT control register (CTRL, offset 0x004) bit description Symbol Value Description Reset value STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur.
Page 244 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 288. SCT limit event select register (LIMIT, offset 0x008) bit description Symbol Description Reset value 15:0 LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, …).
Page 245 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 290. SCT stop event select register (STOP, offset 0x010) bit description Symbol Description Reset value 15:0 STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, …).
Page 246 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.6.9 SCT state register Each group of enabled and disabled events is assigned a number called the state variable. For example, a state variable with a value of 0 could have events 0, 2, and 3 enabled and all other events disabled.
Page 247 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 1. The AIN bit displays the state of the input captured on each rising edge of the SCT clock This corresponds to a nearly direct read-out of the input but can cause spurious fluctuations in case of an asynchronous input signal.
Page 248 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 295. SCT match/capture mode register (REGMODE, offset 0x04C) bit description Symbol Description Reset value 15:0 REGMOD_L Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, …).
Page 249 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 297. SCT bidirectional output control register (OUTPUTDIRCTRL, offset 0x054) bit description Symbol Value Description Reset value SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
Page 250 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 298. SCT conflict resolution register (RES, offset 0x058) bit description …continued Symbol Value Description Reset value O3RES Effect of simultaneous set and clear on output 3. No change. Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
Page 251 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.6.16 SCT event interrupt enable register This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag register (Section 15.6.17) is also set. Table 301. SCT event interrupt enable register (EVEN, offset 0x0F0) bit description...
Page 252 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.6.20 SCT match registers 0 to 9 (REGMODEn bit = 0) Match registers are compared to the counters to help create events. When the UNIFY bit is 0, the L and H registers are independently compared to the L and H counters. When UNIFY is 1, the combined L and H registers hold a 32-bit value that is compared to the unified counter.
Page 253 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 307. SCT match reload registers 0 to 9 (MATCHREL[0:9], offset 0x200 (MATCHREL0) to 0x224 (MATCHREL9)) bit description (REGMODEn bit = 0) Symbol Description Reset value 15:0 RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
Page 254 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 309. SCT event state mask registers 0 to 9 (EV[0:9]_STATE, offsets 0x300 (EV0_STATE) to 0x348 (EV9_STATE)) bit description Symbol Description Reset value 15:0 STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number;...
Page 255 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 310. SCT event control register 0 to 9 (EV[0:9]_CTRL, offset 0x304 (EV0_CTRL) to 0x34C (EV9_CTRL)) bit description Symbol Value Description Reset value 11:10 IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock).
Page 256 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify the state of the outputs when neither counter is halted. This is true regardless of what triggered the event.
Page 257 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.7 Functional description 15.7.1 Match logic Fig 31. Match logic 15.7.2 Capture logic Fig 32. Capture logic 15.7.3 Event selection State variables allow control of the SCT across more than one cycle of the counter.
Page 258 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Fig 33. Event selection 15.7.4 Output generation Figure 34 shows one output slice of the SCT. Fig 34. Output slice i 15.7.5 State logic The SCT can be configured as a timer/counter with multiple programmable states. The states are user-defined through the events that can be captured in each particular state.
Page 259 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) If an event increments the state number beyond the number of available states, the SCT enters a locked state in which all further events are ignored while the counter is still running. Software must interfere to change out of this state.
Page 260 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.7.8 Match vs. I/O events Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock. However, the prescaler and counter are enabled to count only when a selected edge is detected on a clock input.
Page 261 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) • To configure the SCT as simple event controlled counter/timer, see Section 15.7.12. 15.7.10 Configure the SCT To set up the SCT for multiple events and states, perform the following configuration steps: 15.7.10.1 Configure the counter...
Page 262 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) – For each SCT output, select which events set or clear this output. More than one event can change the output, and each event can change multiple outputs. 3. Define how each event affects the counter: –...
Page 263 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.7.11 Run the SCT 1. Configure the SCT (see Section 15.7.10 “Configure the SCT”). 2. Write to the STATE register to define the initial state. By default the initial state is state 3.
Page 264 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.7.13 SCT PWM Example Figure 36 shows a simple application of the SCT using two sets of match events (EV0/1 and EV3/4) to set/clear SCT output 0. The timer is automatically reset whenever it reaches the MAT0 match value.
Page 265 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 314. SCT configuration example Configuration Registers Setting Counter CONFIG Uses one counter (UNIFY = 1). CONFIG Enable the autolimit for MAT0. (AUTOLIMIT = 1.) CTRL Uses unidirectional counter (BIDIR_L = 0).
Page 266 UM10914 NXP Semiconductors Chapter 15: LPC5411x SCTimer/PWM (SCT) Table 314. SCT configuration example Configuration Registers Setting Configure states in which EV3_STATE Set STATEMSK3 bit 1 to 1. Set all other bits to 0. Event 3 is enabled in state 1.
Page 267 UM10914 Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) Rev. 2.0 — 9 May 2018 User manual 16.1 How to read this chapter These five standard timers are available on all LPC5411x devices. 16.2 Features • Each is a 32-bit counter/timer with a programmable 32-bit prescaler. Four of the timers include external capture and match pin connections.
Page 268 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 16.3 Basic configuration • Set the appropriate bits to enable clocks to timers that will be used: CTIMER0 and CTIMER1, and CTIMER2 in the AHBCLKCTRL1 register (Section 6.5.17), CTIMER3...
Page 269 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) Table 316: Suggested CTIMER timer pin settings IOCON Type D pin Type A pin Type I pin bit(s) OD: Set to 0 unless open-drain output is desired. Same as type D.
Page 270 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 16.6.3 Architecture The block diagram for the timers is shown in Figure Fig 37. 32-bit counter/timer block diagram UM10914 All information provided in this document is subject to legal disclaimers.
Page 271 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 16.7 Register description Each Timer/Counter contains the registers shown in Table 317. Table 317. Register overview: CTIMER0/1/2/3 (register base addresses 0x4000 8000 (CTIMER0), 0x4000 9000 (CTIMER1), 0x4002 8000 (CTIMER2), 0x4004 8000 (CTIMER3), 0x4004 9000 (CTIMER4))
Page 272 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 16.7.1 Interrupt Register The Interrupt Register consists of 4 bits for the match interrupts and 4 bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high.
Page 273 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 16.7.4 Prescale register The 32-bit Prescale register specifies the maximum value for the Prescale Counter. Table 321. Timer prescale register (PR, offset 0x0C) bit description Symbol Description Reset value...
Page 274 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) Table 323. Match Control Register (MCR, offset 0x14) bit description Symbol Description Reset Value MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
Page 275 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) Table 325. Capture Control Register (CCR, offset 0x28) bit description Symbol Description Reset Value CAP3RE Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC.
Page 276 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) Table 327. External match register (EMR, offset 0x3C) bit description Symbol Value Description Reset value External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin.
Page 277 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 16.7.11 Count Control Register The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edge(s) for counting.
Page 278 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) Table 328. Count Control Register (CTCR, offset 0x70) bit description Symbol Value Description Reset Value SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared.
Page 279 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) Table 329: PWM Control Register (PWMC, offset 0x74)) bit description Symbol Value Description Reset value PWMEN2 PWM mode enable for channel2. Match. CTIMERn_MAT2 is controlled by EM2. PWM. PWM mode is enabled for CTIMERn_MAT2.
Page 280 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 16.8 Functional description Figure 38 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset.
Page 281 UM10914 NXP Semiconductors Chapter 16: LPC5411x Standard counter/timers (CTIMER0 - 4) 4. If a match register contains the same value as the timer reset value (the PWM cycle length), then the PWM output will be reset to LOW on the next clock tick after the timer reaches the match value.
Page 282 UM10914 Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) Rev. 2.0 — 9 May 2018 User manual 17.1 How to read this chapter The watchdog timer is available on all LPC5411x devices. 17.2 Features • Internally resets chip if not reloaded during the programmable time-out period. •...
Page 283 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) 17.3 Basic configuration Configuration of the WWDT is accomplished as follows: • Turn on and configure the Watchdog oscillator. See the PDEN_WDT_OSC bit in the PDRUNCG0 register (Section 6.5.51), and the Watchdog oscillator control register (Section 6.5.47).
Page 284 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) • Enable and configure the Watchdog oscillator as described in Section 17.3 “Basic configuration” • Set the Watchdog timer constant reload value in the TC register. • Set the Watchdog timer operating mode in the MOD register.
Page 285 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) Fig 42. Windowed Watchdog timer block diagram 17.5.2 Clocking and power control The watchdog timer block uses two clocks: APB bus clock and WDCLK. The APB bus clock is used for the APB accesses to the watchdog registers and is derived from the...
Page 286 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) 17.5.3 Using the WWDT lock features The WWDT supports several lock features which can be enabled to ensure that the WWDT is running at all times: • Disabling the WWDT clock source •...
Page 287 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) 17.6 Register description The Watchdog Timer contains the registers shown in Table 330. The reset value reflects the data stored in used bits only. It does not include the content of reserved bits.
Page 288 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) Table 331. Watchdog mode register (MOD, offset 0x000) bit description Symbol Value Description Reset value WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
Page 289 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) 17.6.2 Watchdog Timer Constant register The TC register determines the time-out value. A feed sequence is required to transfer the TC value into the Watchdog counter. The TC resets to 0x00 00FF. Writing a value below 0xFF will cause 0x00 00FF to be loaded into the TC.
Page 290 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) Table 335. Watchdog Timer Value register (TV, offset 0x0C) bit description Symbol Description Reset value 23:0 COUNT Counter timer value. 0x00 00FF 31:24 Reserved. Read value is undefined, only zero should be written. - 17.6.5 Watchdog Timer Warning Interrupt register...
Page 291 UM10914 NXP Semiconductors Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) 17.7 Functional description The following figures illustrate several aspects of Watchdog Timer operation. Fig 43. Early watchdog feed with windowed mode enabled Fig 44. Correct watchdog feed with windowed mode enabled Fig 45.
Page 292 UM10914 Chapter 18: LPC5411x Real-Time Clock (RTC) Rev. 2.0 — 9 May 2018 User manual 18.1 How to read this chapter The RTC is available on all LPC5411x devices. 18.2 Features • The RTC and its independent oscillator operate directly from the device power pins, not using the on-chip regulator.
Page 293 UM10914 NXP Semiconductors Chapter 18: LPC5411x Real-Time Clock (RTC) Fig 46. RTC clocking 18.3.1 RTC timers The RTC contains two timers: 1. The main RTC timer. This 32-bit timer uses a 1 Hz clock and is intended to run continuously as a real-time clock. When the timer value reaches a match value, an interrupt is raised.
Page 294 UM10914 NXP Semiconductors Chapter 18: LPC5411x Real-Time Clock (RTC) 18.5 General description 18.5.1 Real-time clock The real-time clock is a 32-bit up-counter which can be cleared or initialized by software. Once enabled, it counts continuously at a 1 Hz clock rate as long as the device is powered up and the RTC remains enabled.
Page 295 UM10914 NXP Semiconductors Chapter 18: LPC5411x Real-Time Clock (RTC) 18.6 Register description Reset Values pertain to initial power-up of the device or when an RTC software reset is applied (except where noted). This block is not initialized by any other system reset.
Page 296 UM10914 NXP Semiconductors Chapter 18: LPC5411x Real-Time Clock (RTC) Table 340. RTC control register (CTRL, offset 0x000) bit description Symbol Value Description Reset value WAKEDPD_EN RTC 1 kHz timer wake-up enable for deep power-down. Disable. A match on the 1 kHz RTC timer will not bring the part out of deep power-down mode.
Page 297 UM10914 NXP Semiconductors Chapter 18: LPC5411x Real-Time Clock (RTC) 18.6.4 RTC high-resolution/wake-up register Table 343. RTC high-resolution/wake-up register (WAKE, offset 0x0C) bit description Symbol Description Reset value 15:0 A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence.
Page 298 UM10914 Chapter 19: LPC5411x Multi-Rate Timer (MRT) Rev. 2.0 — 9 May 2018 User manual 19.1 How to read this chapter The MRT is available on all LPC5411x parts. 19.2 Features • 24-bit interrupt timer • Four channels independently counting down from individually set values •...
Page 299 UM10914 NXP Semiconductors Chapter 19: LPC5411x Multi-Rate Timer (MRT) Fig 47. MRT block diagram 19.5.1 Repeat interrupt mode The repeat interrupt mode generates repeated interrupts after a selected time interval. This mode can be used for software-based PWM or PPM applications.
Page 300 UM10914 NXP Semiconductors Chapter 19: LPC5411x Multi-Rate Timer (MRT) • Update the INTVALn register with a new time interval value (>0) and set the LOAD bit to 1. The timer immediately reloads the new time interval, and starts counting down from the new value.
Page 301 UM10914 NXP Semiconductors Chapter 19: LPC5411x Multi-Rate Timer (MRT) 19.6 Register description The reset values shown in Table 344 are POR reset values. Table 344. Register overview: MRT (base address 0x4000 D000) Name Access Offset Description Reset value Section MRT Timer 0 registers INTVAL0 MRT0 Time interval value.
Page 302 UM10914 NXP Semiconductors Chapter 19: LPC5411x Multi-Rate Timer (MRT) 19.6.1 Time interval register This register contains the MRT load value and controls how the timer is reloaded. The load value is IVALUE -1. Table 345. Time interval register (INTVAL[0:3], offset 0x000 (INTVAL0) to 0x030 (INTVAL3)) bit description...
Page 303 UM10914 NXP Semiconductors Chapter 19: LPC5411x Multi-Rate Timer (MRT) 19.6.3 Control register The control register configures the mode for each MRT and enables the interrupt. Table 347. Control register (CTRL[0:3], offset 0x08 (CTRL0) to 0x38 (CTRL3)) bit description Symbol Value...
Page 304 UM10914 NXP Semiconductors Chapter 19: LPC5411x Multi-Rate Timer (MRT) 19.6.5 Module Configuration register The MODCFG register provides the configuration (number of channels and timer width) for this MRT. See Section 19.6.6 “Idle channel register” for details. Table 349. Module Configuration register (MODCFG, offset 0xF0) bit description...
Page 305 UM10914 NXP Semiconductors Chapter 19: LPC5411x Multi-Rate Timer (MRT) 19.6.7 Global interrupt flag register The global interrupt register combines the interrupt flags from the individual timer channels in one register. Setting and clearing each flag behaves in the same way as setting and clearing the INTFLAG bit in each of the STATUSn registers.
Page 306 UM10914 Chapter 20: LPC5411x CPU system tick timer (SYSTICK) Rev. 2.0 — 9 May 2018 User manual 20.1 How to read this chapter The system tick timer (SysTick timer) is present on all LPC5411x devices in both the Arm Cortex-M4 and Arm Cortex-M0+ cores (when the Cortex-M0+ is present on selected devices).
Page 307 UM10914 NXP Semiconductors Chapter 20: LPC5411x CPU system tick timer (SYSTICK) 20.4 General description Block diagrams of the SysTick timer for each CPU is shown in Figure Fig 48. System tick timer block diagram The SysTick timer is an integral part of both the Cortex-M4 and Cortex-M0+ (if present).
Page 308 UM10914 NXP Semiconductors Chapter 20: LPC5411x CPU system tick timer (SYSTICK) 20.5 Register description The systick timer registers are located on the private peripheral bus of each CPU (see Figure Table 352. Register overview: SysTick timer (base address 0xE000 E000)
Page 309 UM10914 NXP Semiconductors Chapter 20: LPC5411x CPU system tick timer (SYSTICK) 20.5.3 System Timer Current value register The SYST_CVR register returns the current count from the System Tick counter when it is read by software. Table 355. System Timer Current value register (SYST_CVR, offset 0x018) bit description...
Page 310 UM10914 NXP Semiconductors Chapter 20: LPC5411x CPU system tick timer (SYSTICK) 20.6 Functional description The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts. The...
Page 311 UM10914 Chapter 21: LPC5411x Micro-tick Timer (UTICK) Rev. 2.0 — 9 May 2018 User manual 21.1 How to read this chapter The Micro-Tick Timer is available on all LPC5411x devices. 21.2 Features • Ultra simple, ultra-low power timer that can run and wake up the device in reduced power modes other than deep power-down.
Page 312 UM10914 NXP Semiconductors Chapter 21: LPC5411x Micro-tick Timer (UTICK) 21.5 General description Figure 49 shows a conceptual view of the Micro-tick Timer. Fig 49. MIcro-Tick Timer block diagram UM10914 All information provided in this document is subject to legal disclaimers.
Page 313 UM10914 NXP Semiconductors Chapter 21: LPC5411x Micro-tick Timer (UTICK) 21.6 Register description The Micro-Tick Timer contains the registers shown in Table 358. Note that the Micro-Tick Timer operates from a different (typically slower) clock than the CPU and bus systems.
Page 314 UM10914 NXP Semiconductors Chapter 21: LPC5411x Micro-tick Timer (UTICK) Table 361. Capture configuration register (CFG, offset 0x008) bit description Symbol Description Reset value CAPEN0 Enable Capture 0. 1 = Enabled, 0 = Disabled. CAPEN1 Enable Capture 1. 1 = Enabled, 0 = Disabled.
Page 315 UM10914 Chapter 22: LPC5411x USB 2.0 device controller Rev. 2.0 — 9 May 2018 User manual 22.1 How to read this chapter The USB block is available on selected LPC5411x devices. 22.2 Features • USB2.0 full-speed device controller. • Supports 10 physical (5 logical) endpoints including two control endpoints if physical, one control endpoint if logical.
Page 316 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.5 General description The Universal Serial Bus (USB) is a four-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol.
Page 317 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional USB0_DP and USB0_DM signals of the USB bus. The SIE implements the full USB protocol layer. It is completely hard-wired for speed and needs no software intervention.
Page 318 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.5.1 USB software interface USB EP List Start Address EP_LIST 0x00 CS = Endpoint Control /Status bits SRAM NBytes ADDR OFFSET 1 NBytes ADDR OFFSET 2 USB Data Buffer Start Address...
Page 319 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Software can control the pull-up by setting the DCON bit in the DEVCMDSTAT register. If the DCON bit is set to 1, the USB_DP line is pulled up to VDD through an internal 1.5 KOhm pull-up resistor.
Page 320 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.5.7 Clocking The USB device controller has the following clock connections: • USB main clock: The USB main clock is a 48 MHz clock used for USB functions (see Section 6.5.27 Section 6.5.37).
Page 321 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.6 Register description Table 366. Register overview: USB (base address 0x4008 4000) Name Access Offset Description Reset value Section DEVCMDSTAT 0x000 USB Device Command/Status register 0x800 22.6.1 INFO 0x004 USB Info register 22.6.2...
Page 322 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Table 367. USB Device Command/Status register (DEVCMDSTAT, offset 0x00) bit description Symbol Value Description Reset Access value INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP Only acknowledged packets generate an interrupt Both acknowledged and NAKed packets generate interrupts.
Page 323 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Table 367. USB Device Command/Status register (DEVCMDSTAT, offset 0x00) bit description Symbol Value Description Reset Access value DSUS_C Device status - suspend change. R/W1C The suspend change bit is set to 1 when the suspend bit toggles.
Page 324 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Table 368. USB Info register (INFO, offset 0x04) bit description Symbol Value Description Reset value Access 14:11 ERR_CODE The error code which last occurred: No error PID encoding error PID unknown...
Page 325 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.6.5 USB Link Power Management register Table 371. Link Power Management register (LPM, offset 0x10) bit description Symbol Description Reset Access value HIRD_HW Host Initiated Resume Duration - HW. This is the HIRD value from the last...
Page 326 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.6.8 USB Endpoint Buffer Configuration Table 374. USB Endpoint Buffer Configuration (EPBUFCFG, offset 0x1C) bit description Symbol Description Reset value Access Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint.
Page 327 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Table 375. USB interrupt status register (INTSTAT, offset 0x20) bit description Symbol Description Reset Access value EP3OUT Interrupt status register bit for the EP3 OUT direction. R/W1C This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.
Page 328 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.6.11 USB set interrupt status register Table 377. USB set interrupt status register (INTSETSTAT, offset 0x28) bit description Symbol Description Reset value Access EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
Page 329 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.7 Functional description 22.7.1 Endpoint command/status list Figure 52 gives an overview on how the Endpoint List is organized in memory. The USB EP Command/Status List start register points to the start of the list that contains all the endpoint information in memory.
Page 330 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Table 379. Endpoint commands Symbol Access Description Active The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint.
Page 331 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Table 379. Endpoint commands Symbol Access Description Endpoint Type 0: Generic endpoint. The endpoint is configured as a bulk or interrupt endpoint. 1: Isochronous endpoint NBytes For OUT endpoints this is the number of bytes that can be received in this buffer.
Page 332 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 22.7.2 Control endpoint 0 Wait on EP 0Setup /Out interrupt EP0Setup/Out Interrupt = ‘1’ ? If not all IN data transferred , the - Write EP0OUT(Active = ‘1’ host aborts Control Read .
Page 333 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Wait on EP 0In interrupt EP0In Interrupt = ‘1’ ? If not all OUT data transferred , the host aborts Control Write . - Write EP0IN( Active = ‘1’ Otherwise it is a normal completion Stall = ‘1’...
Page 334 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller Software must wait until hardware has cleared the Active bit to change some of the command/status bits. This prevents hardware from overwriting a new value programmed by software with some old values that were still cached.
Page 335 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller • Set the STALL bit of both buffer 0 and buffer 1 to 0. • Read the buffer in use bit for this endpoint. • Set the toggle reset bit (TR) to 1 and set the toggle value bit (TV) to 0 for the buffer indicated by the buffer in use bit.
Page 336 UM10914 NXP Semiconductors Chapter 22: LPC5411x USB 2.0 device controller 5. Wait until the USB leaves the suspend state by polling the DSUS bit in the DSVCMD_STAT register (DSUS =0). 6. Clear the FORCE_NEEDCLK bit (Section 22.6.1, bit 0) in the DEVCMDSTAT to enable automatic USB clock control.
Page 337 UM10914 Chapter 23: LPC5411x Flexcomm Interface serial communication Rev. 2.0 — 9 May 2018 User manual 23.1 How to read this chapter Multiple Flexcomm Interfaces are available on all LPC5411x parts. 23.2 Introduction Each Flexcomm Interface provides one peripheral function from a choice of several, chosen by the user.
Page 338 UM10914 NXP Semiconductors Chapter 23: LPC5411x Flexcomm Interface serial communication 23.5 Pin description Each Flexcomm Interface allows up to 7 pin connections. Specific uses of a Flexcomm Interface typically do not use all of these, and some Flexcomm Interface instances may not provide a means to connect all functions to device pins.
Page 339 UM10914 NXP Semiconductors Chapter 23: LPC5411x Flexcomm Interface serial communication 23.6 General description The overall structure of one Flexcomm Interface is shown in Figure Fig 55. Flexcomm Interface block diagram 23.6.1 Function Summary LPC5411x devices include Flexcomm Interfaces and functions as shown in Table 381.
Page 340 UM10914 NXP Semiconductors Chapter 23: LPC5411x Flexcomm Interface serial communication 23.6.4 DMA The Flexcomm Interface generates DMA requests if desired, based on a selectable FIFO level. Refer to the chapter for a specific peripheral function for information on how the...
Page 341 UM10914 NXP Semiconductors Chapter 23: LPC5411x Flexcomm Interface serial communication 23.7 Register description Each Flexcomm Interface contains registers that are related to configuring the Flexcomm Interface to do a specific peripheral function and other registers related to peripheral FIFOs and data access. The latter depend somewhat on the chosen peripheral functions...
Page 342 UM10914 NXP Semiconductors Chapter 23: LPC5411x Flexcomm Interface serial communication Table 383. Peripheral Select and Flexcomm Interface ID register (PSELID - offset 0xFF8) bit description Symbol Value Description Reset Value I2SPRESENT S present indicator. This field is Read-only. This Flexcomm Interface does not include the I S function.
Page 343 UM10914 Chapter 24: LPC5411x USARTs Rev. 2.0 — 9 May 2018 User manual 24.1 How to read this chapter USART functions are available on all LPC5411x devices as a selectable function in each Flexcomm Interface peripheral. Up to 8 Flexcomm Interfaces are available. 24.2 Features •...
Page 344 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs • Select the desired Flexcomm Interface function by writing to the PSELID register of the related Flexcomm Interface (Section 23.7.1). • Configure the FIFOs for operation. • Configure USART for receiving and transmitting data: –...
Page 345 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs For details on the clock configuration see: Section 24.7.2 “Clocking and baud rates” 24.3.2 Configure the USART for wake-up A USART can wake up the system from sleep mode in asynchronous or synchronous mode on any enabled USART interrupt.
Page 346 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs • Set up the appropriate USART function to use DMA, and set the related WAKE bit (WAKETX for the transmit function, and WAKERX for the receive function) in the FIFOCFG register. • Configure the DMA controller appropriately, including a transfer complete interrupt.
Page 347 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.4 Pin description The USART receive, transmit, and control signals are movable Flexcomm Interface functions and are assigned to external pins through via IOCON. See the IOCON description (Chapter 9) to assign the USART functions to pins on the device package.
Page 348 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.5 General description The USART receiver block monitors the serial input line, Un_RXD, for valid input. The receiver shift register assembles characters as they are received, after which they are passed to the receiver FIFO to await access by the CPU or DMA controller.
Page 349 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.6 Register description The reset value reflects the data stored in used bits only. It does not include the content of reserved bits. Address offsets are within the related Flexcomm Interface address space after the USART function has been selected for that Flexcomm Interface (see Section 23.6.1...
Page 350 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.6.1 USART Configuration register The CFG register contains communication and mode settings for aspects of the USART that would normally be configured once in an application. Remark: Only the CFG register can be written when the ENABLE bit = 0. CFG can be set up by software with ENABLE = 1, then the rest of the USART can be configured.
Page 351 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 388. USART Configuration register (CFG, offset 0x000) bit description …continued Symbol Value Description Reset Value CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART’s own RTS if loopback mode is enabled.
Page 352 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 388. USART Configuration register (CFG, offset 0x000) bit description …continued Symbol Value Description Reset Value RXPOL Receive data polarity. Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
Page 353 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 389. USART Control register (CTL, offset 0x004) bit description Symbol Value Description Reset Value Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
Page 354 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 390. USART Status register (STAT, offset 0x008) bit description Symbol Description Reset Access value RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing.
Page 355 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 391. USART Interrupt Enable read and set register (INTENSET, offset 0x00C) bit description …continued Symbol Description Reset Value STARTEN When 1, enables an interrupt when a received start bit has been detected.
Page 356 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Remark: To change a baud rate after a USART is running, the following sequence should be used: 1. Make sure the USART is not currently sending or receiving data. 2. Disable the USART by writing a 0 to the Enable bit (0 may be written to the entire register).
Page 357 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Changing the oversampling can sometimes allow better matching of baud rates in cases where the function clock rate is not a multiple of 16 times the expected maximum baud rate. For all modes where the OSR setting is used, the USART receiver takes three consecutive samples of input data in the approximate middle of the bit time.
Page 358 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.6.10 FIFO Configuration register This register configures FIFO usage. A peripheral function within the Flexcomm Interface must be selected prior to configuring the FIFO. Table 397. FIFO Configuration register (FIFOCFG - offset 0xE00) bit description...
Page 359 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 397. FIFO Configuration register (FIFOCFG - offset 0xE00) bit description Symbol Value Description Reset Access value EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
Page 360 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.6.12 FIFO trigger level settings register This register allows selecting when FIFO-level related interrupts occur. Table 399. FIFO trigger level settings register (FIFOTRIG - offset 0xE08) bit description Symbol Value Description Reset value TXLVLENA Transmit FIFO level trigger enable.
Page 361 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 400. FIFO interrupt enable set and read register (FIFOINTENSET - offset 0xE10) bit description Symbol Value Description Reset value TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
Page 362 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 402. FIFO interrupt status register (FIFOINTSTAT - offset 0xE18) bit description Symbol Description Reset value TXERR TX FIFO error. RXERR RX FIFO error. TXLVL Transmit FIFO level interrupt. RXLVL Receive FIFO level interrupt.
Page 363 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Table 405. FIFO data read with no FIFO pop (FIFORDNOPOP - offset 0xE40) bit description Symbol Description Reset value PARITYERR Parity Error status flag. RXNOISE Received Noise flag. 31:16 Reserved, the value read from a reserved bit is not defined.
Page 364 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.7 Functional description 24.7.1 AHB bus access The bus interface to the USART registers contained in the Flexcomm Interface support only word writes. Byte and halfword writes are not supported in conjunction with the USART function.
Page 365 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs data bit must be reduced to one. Finally, special clocking has to be used for individual bit times because 32 kHz is not particularly close to an integer multiple of any standard baud rate.
Page 366 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Fig 57. Hardware flow control using RTS and CTS 24.7.5.2 Software flow control Software flow control could include XON / XOFF flow control, or other mechanisms. these are supported by the ability to check the current state of the CTS input, and/or have an...
Page 367 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs 24.7.8 Oversampling Typical industry standard USARTs use a 16x oversample clock to transmit and receive asynchronous data. This is the number of BRG clocks used for one data bit. The Oversample Select Register (OSR) allows this USART to use a 16x down to a 5x oversample clock.
Page 368 UM10914 NXP Semiconductors Chapter 24: LPC5411x USARTs Wake-up for LIN can potentially be handled in a number of ways, depending on the system, and what clocks may be running in a slave device. For instance, as long as the USART is receiving internal clocks allowing it to function, it can be set to wake up the CPU for any interrupt, including a received start bit.
Page 369 UM10914 Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Rev. 2.0 — 9 May 2018 User manual 25.1 How to read this chapter SPI functions are available on all LPC5411x devices as a selectable function in each Flexcomm Interface peripheral. Up to 8 Flexcomm Interfaces are available. 25.2 Features •...
Page 370 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.3.1 Configure the SPI for wake-up In sleep mode, any signal that triggers an SPI interrupt can wake up the part, provided that the interrupt is enabled in the INTENSET register and the NVIC. As long as the SPI clock is configured to be active in sleep mode, the SPI can wake up the part independently of whether the SPI block is configured in master or slave mode.
Page 371 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.4 Pin description The SPI signals are movable Flexcomm Interface functions and are assigned to external pins via IOCON. Table 407: SPI Pin Description Function Type Pin name used in Pin...
Page 372 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 408: Suggested SPI pin settings IOCON Type D pin Type A pin Type I pin bit(s) OD: Set to 0 unless open-drain output is desired. Same as type D.
Page 373 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.6 Register description Address offsets are within the address space of the related Flexcomm Interface. The Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Page 374 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.6.1 SPI Configuration register The CFG register contains information for the general configuration of the SPI. Typically, this information is not changed during operation. See the description of the master idle...
Page 375 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 410. SPI Configuration register (CFG, offset 0x400) bit description …continued Symbol Value Description Reset value SPOL0 SSEL0 Polarity select. Low. The SSEL0 pin is active low. High. The SSEL0 pin is active high.
Page 376 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 411. SPI Delay register (DLY, offset 0x404) bit description Symbol Description Reset value PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data transfer.
Page 377 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 412. SPI Status register (STAT, offset 0x408) bit description Symbol Description Reset Access value Reserved. Read value is undefined, only zero should be written. Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes.
Page 378 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 413. SPI Interrupt Enable read and Set register (INTENSET, offset 0x40C) bit description Symbol Value Description Reset value Reserved. Read value is undefined, only zero should be written. MSTIDLEEN Master idle interrupt enable.
Page 379 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 416. SPI Interrupt Status register (INTSTAT, offset 0x428) bit description Symbol Description Reset value Reserved. Read value is undefined, only zero should be written. - MSTIDLE Master Idle status flag.
Page 380 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.6.8 FIFO Configuration register This register configures FIFO usage. A peripheral function within the Flexcomm Interface must be selected prior to configuring the FIFO. Table 417. FIFO Configuration register (FIFOCFG - offset 0xE00) bit description...
Page 381 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 417. FIFO Configuration register (FIFOCFG - offset 0xE00) bit description Symbol Value Description Reset Access value EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
Page 382 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.6.10 FIFO trigger settings register This register allows selecting when FIFO-level related interrupts occur. Table 419. FIFO trigger settings register (FIFOTRIG - offset 0xE08) bit description Symbol Value Description Reset...
Page 383 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.6.11 FIFO interrupt enable set and read This register is used to enable various interrupt sources. The complete set of interrupt enables may be read from this register. Writing ones to implemented bits in this register causes those bits to be set.
Page 384 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.6.13 FIFO interrupt status register The read-only FIFOINTSTAT register provides a view of those interrupt flags that are both pending and currently enabled. This can simplify software handling of interrupts. Refer to the descriptions of interrupts in Section 25.6.9...
Page 385 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 423. FIFO write data register (FIFOWR - offset 0xE20) bit description Symbol Value Description Reset value TXSSEL2_N Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
Page 386 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Table 424. FIFO read data register (FIFORD - offset 0xE30) bit description Symbol Description Reset value 15:0 RXDATA Received data from the FIFO. RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data.
Page 387 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.6.17 Module identification register The ID register identifies the type and revision of the SPI module. A generic SW driver can make use of this information register to implement module type or revision specific behavior.
Page 388 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.7 Functional description 25.7.1 AHB bus access With the exception of the FIFOWR register, the bus interface to the SPI registers contained in the Flexcomm Interface support only word writes. Byte and halfword writes are not supported in conjunction with the SPI function for those registers.
Page 389 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Fig 59. Basic SPI operating modes UM10914 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. User manual Rev. 2.0 — 9 May 2018...
Page 390 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.7.3 Frame delays Several delays can be specified for SPI frames. These include: • Pre_delay: delay after SSEL is asserted before data clocking begins • Post_delay: delay at the end of a data frame before SSEL is deasserted •...
Page 391 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.7.3.2 Frame_delay The Frame_delay value controls the amount of time at the end of each frame. This delay is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in Figure Note that frame boundaries occur only where specified.
Page 392 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.7.3.3 Transfer_delay The Transfer_delay value controls the minimum amount of time that SSEL is deasserted between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be deasserted for a minimum of one SPI clock time.
Page 393 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.7.4 Clocking and data rates In order to use the SPI, clocking details must be defined. This includes configuring the system clock and selection of the clock divider value in DIV. See Figure 9 “Clock...
Page 394 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.7.6 DMA operation A DMA request is provided for each SPI direction, and can be used in lieu of interrupts for transferring data by configuring the DMA controller appropriately. The DMA controller provides an acknowledgement signal that clears the related request when it completes handling that request.
Page 395 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Write both data and control bits to FIFOWR for all data. The control bits for the last entry would include the setting of the EOT bit. This also allows a series of SPI transactions involving multiple slaves with one DMA operation, by changing the TXSSELn_N bits.
Page 396 UM10914 NXP Semiconductors Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) Fig 63. Examples of data stalls UM10914 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved. User manual Rev. 2.0 — 9 May 2018...
Page 397 UM10914 Chapter 26: LPC5411x I C-bus interfaces Rev. 2.0 — 9 May 2018 User manual 26.1 How to read this chapter C-bus functions are available on all LPC5411x devices as a selectable function in each Flexcomm Interface peripheral. Up to 8 Flexcomm Interfaces are available. 26.2 Features •...
Page 398 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces – Configure the related Flexcomm Interface pin functions via IOCON, see Chapter – Configure the I C clock and data rate. This includes the CLKDIV register for both master and slave modes, and MSTTIME for master mode. Also see Section 26.6.6...
Page 399 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces – The I C master sends the data bits to the slave address. 6. Wait for the pending status to be set (MSTPENDING = 1) by polling the STAT register. 7. Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register.
Page 400 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 429. Code example Master read from slave // Master read 1 byte from slave. Address 0x23. Polling mode. No error checking. uint8_t data; I2C->CFG = I2C_CFG_MSTEN; while(!(I2C->STAT & I2C_STAT_MSTPENDING)); if((I2C->STAT & I2C_STAT_MSTSTATE) != I2C_STAT_MSTST_IDLE) abort();...
Page 401 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 430. Code example Slave read from master //Slave read 1 byte from master. Address 0x23. Polling mode. uint8_t data; I2C->SLVADR0 = 0x23 << 1; // put address in address 0 register I2C->CFG = I2C_CFG_SLVEN;...
Page 402 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.3.3 Configure the I C for wake-up In sleep mode, any activity on the I C-bus that triggers an I C interrupt can wake up the part, provided that the interrupt is enabled in the INTENSET register and the NVIC. As...
Page 403 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.4 Pin description The I C pins are fixed-pin functions and enabled through IOCON. Refer to the IOCON settings in Table 433 and in Section 9.5.2. Table 432. I C-bus pin description...
Page 404 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.6 Register description Address offsets are within the address space of the related Flexcomm Interface. The Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Page 405 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.6.1 I2C Configuration register The CFG register contains mode settings that apply to Master, Slave, and Monitor functions. Table 435. I C Configuration register (CFG, offset 0x800) bit description Symbol Value Description...
Page 406 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.6.2 I2C Status register The STAT register provides status flags and state information about all of the functions of the I C interface. Access to bits in this register varies. RO = Read-only, W1C = write 1 to clear.
Page 407 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 436. I C Status register (STAT, offset 0x804) bit description …continued Symbol Value Description Reset Access value MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically when a 1 is written to MSTCONTINUE.
Page 408 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 436. I C Status register (STAT, offset 0x804) bit description …continued Symbol Value Description Reset Access value 13:12 SLVIDX Slave address match Index. This field is valid when the I...
Page 409 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 436. I C Status register (STAT, offset 0x804) bit description …continued Symbol Value Description Reset Access value MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the C-bus change from active to inactive.
Page 410 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 438. Slave function state codes (SLVSTATE) SLVSTATE Description Actions allowed 0 SLVST_ADDR Address plus R/W received. At Software can further check the address if needed, for least one of the 4 slave addresses instance if a subset of addresses qualified by SLVQUAL0 has been matched by hardware.
Page 411 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 439. Interrupt Enable Set and read register (INTENSET, offset 0x808) bit description Symbol Value Description Reset value MONRDYEN Monitor data Ready interrupt Enable. Disabled. The MonRdy interrupt is disabled. Enabled. The MonRdy interrupt is enabled.
Page 412 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 440. Interrupt Enable Clear register (INTENCLR, offset 0x80C) bit description …continued Symbol Description Reset value MONIDLECLR Monitor Idle interrupt clear. 23:20 - Reserved. Read value is undefined, only zero should be written.
Page 413 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 442. I C Clock Divider register (CLKDIV, offset 0x814) bit description Symbol Description Reset value 15:0 DIVVAL This field controls how the Flexcomm Interface clock (FCLK) is used by the I C functions that need an internal clock in order to operate.
Page 414 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.6.8 Master Control register The MSTCTL register contains bits that control various functions of the I C Master interface. Only write to this register when the master is pending (MSTPENDING = 1 in the...
Page 415 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.6.9 Master Time register The MSTTIME register allows programming of certain times that may be controlled by the Master function. These include the clock (SCL) high and low times, repeated Start setup time, and transmitted data setup time.
Page 416 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 446. Master Data register (MSTDAT, offset 0x828) bit description Symbol Description Reset value DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
Page 417 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 447. Slave Control register (SLVCTL, offset 0x840) bit description Symbol Value Description Reset Value AUTOACK Automatic Acknowledge.When this bit is set, it will cause an I C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately;...
Page 418 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 449. Slave Address 0 register (SLVADR[0], offset 0x848) bit description Symbol Value Description Reset value SADISABLE0 Slave Address 0 Disable. Enabled. Slave Address 0 is enabled. Ignored Slave Address 0 is ignored.
Page 419 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 451. Slave address Qualifier 0 register (SLVQUAL0, offset 0x858) bit description Symbol Value Description Reset Value QUALMODE0 Qualify mode for slave address 0. Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
Page 420 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 452. Monitor data register (MONRXDAT, offset 0x880) bit description Symbol Value Description Reset value MONNACK Monitor Received NACK. Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
Page 421 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.7 Functional description 26.7.1 AHB bus access The bus interface to the I C registers contained in the Flexcomm Interface support only word writes. Byte and halfword writes are not supported in conjunction with the I function.
Page 422 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Table 454. Settings for 400 kHz clock rate Input clock to I2C DIVVAL for CLKDIV MSTSCLHIGH for MSTTIME MSTSCLLOW for MSTTIME register register register 96 MHz 48 MHz 48 MHz 30 MHz...
Page 423 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces For software consistency, the changes required for handling of acknowledge and address recognition, and which affect when interrupts occur, are always in effect when the I C is configured to be HS capable. This means that software does not need to know if a particular transfer is actually in HS mode or not.
Page 424 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces any of these events is longer than the time configured in the TIMEOUT register. This time-out could be useful in monitoring an I C-bus within a system as part of a method to keep the bus running of problems occur.
Page 425 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces 26.7.6 lnterrupt handling The I C provides a single interrupt output that handles all interrupts for Master, Slave, and Monitor functions. 26.7.7 DMA DMA with the I C is done only for data transfer, DMA cannot handle control of the I Once DMA is transferring data, I C acknowledges are handled implicitly.
Page 426 UM10914 NXP Semiconductors Chapter 26: LPC5411x I C-bus interfaces Software will be invoked to handle any exceptions to the standard transfer. 26.7.7.3 DMA as a Slave transmitter A basic sequence for a Slave transmitter: • Software acknowledges an I C address.
Page 427 UM10914 Chapter 27: LPC5411x I S interface Rev. 2.0 — 9 May 2018 User manual 27.1 How to read this chapter I2S functionality is available on all LPC5411x devices. I S is a function that is implemented in selected Flexcomm Interface peripherals. In the LPC5411x, the I function is included in Flexcomm Interface 6 and Flexcomm Interface 7.
Page 428 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface • Sampling frequencies supported depends on the specific device configuration and applications constraints (e.g. system clock frequency, PLL availability, etc.) but generally supports standard audio data rates. 27.3 Basic configuration Initial configuration of the I S peripheral is accomplished as follows: 1.
Page 429 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface • Any enabled I2S interrupt wakes up the part from sleep mode. 27.3.1.2 Wake-up from deep-sleep mode • Configure the I2S for the desired mode and other operational details, see Table 459 Table 460.
Page 430 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.4 General description The overall architecture of an example I S subsystem is shown in Figure Fig 65. I S block diagram 27.4.1 Terminology Table 456: List of some terminology used in this document...
Page 431 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.5 Pin description Remark: When the I S function is outputting SCK and/or WS, it uses a return signal from the related pin to adjust internal timing. For that reason, those signals must in fact be connected to a device pin, via IOCON selection, in order for the I S to operate.
Page 432 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6 Register description The registers shown in Table 458 apply if the I S function is selected in a Flexcomm Interface that supports I The reset value reflects the value of defined bits only, and does not include reserved bits.
Page 433 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.1 Configuration register 1 The CFG1 register contains mode settings, most of which apply to all I S channel pairs within one Flexcomm Interface. A few settings apply only to the primary channel pair, as noted.
Page 434 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface Table 459. Configuration register 1 (CFG1 - offset 0xC00) bit description Symbol Value Description Reset Value MODE Selects the basic I S operating mode. Other configurations modify this to obtain all supported cases.
Page 435 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface Table 459. Configuration register 1 (CFG1 - offset 0xC00) bit description Symbol Value Description Reset Value PDMDATA PDM Data selection. This bit controls the data source for I S transmit, and cannot be set in Rx mode.
Page 436 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.2 Configuration register 2 The CFG2 register contains bits that control various aspects of data configuration. Table 460. Configuration register 2 (CFG2 - offset 0xC04) bit description Symbol Description Reset Value FRAMELEN Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in.
Page 437 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.3 Status register The STAT register provides status flags for the I S function, and does not include FIFO status. Note that the FIFO status register supplies peripheral interrupt notification and would be the status register normally observed first for an interrupt service.
Page 438 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface Table 462. Clock Divider register (DIV - offset 0xC1C) bit description Symbol Description Reset Value 11:0 This field controls how this I S block uses the Flexcomm Interface function clock. 0x000 = The Flexcomm Interface function clock is used directly.
Page 439 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface Table 463. FIFO Configuration register (FIFOCFG - offset 0xE00) bit description Symbol Value Description Reset Access Value DMATX DMA configuration for transmit. DMA is not used for the transmit function. Generate a DMA request for the transmit function if the FIFO is not full.
Page 440 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.6 FIFO status register This register provides status information for the FIFO and also indicates an interrupt from the peripheral function. Remark: Since all I S channels in a single Flexcomm Interface move data in the same direction, only TX related or RX related flags and controls are meaningful at any particular time.
Page 441 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.7 FIFO trigger settings register This register allows selecting when FIFO-level related interrupts occur. Remark: Since all I S channels in a single Flexcomm Interface move data in the same direction, only TX related or RX related flags and controls are meaningful at any particular time.
Page 442 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.8 FIFO interrupt enable set and read This register is used to enable various interrupt sources. The complete set of interrupt enables may be read from this register. Writing ones to implemented bits in this register causes those bits to be set.
Page 443 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.10 FIFO interrupt status register The read-only FIFOINTSTAT register provides a view of those interrupt flags that are both pending and currently enabled. This can simplify software handling of interrupts. Refer to the descriptions of interrupts in Section 27.6.6...
Page 444 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.13 FIFO read data register The FIFORD register is used to read values that have been received by the FIFO. Details of how FIFORD and FIFORD48H are used can be found in Section 27.7.4 “FIFO buffer...
Page 445 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.6.17 Module identification register The ID register identifies the type and revision of the module. A generic SW driver can make use of this information register to implement module type or revision specific behavior.
Page 446 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.7 Functional description 27.7.1 AHB bus access The bus interface to the I S registers contained in the Flexcomm Interface support only word writes. Byte and halfword writes are not supported in conjunction with the I function.
Page 447 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.7.2.2 Example frame configurations A sampling of frame slot formats are shown in the following figures. This is not an exhaustive set of possibilities, but shows the various frame formatting concepts. Note that slot identifications are illustrative only, data positions are flexible and there are no predefined slots for the hardware.
Page 448 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface MODE = 0; SCK_POL = 0; WS_POL = 0; MONO = 0 POSITION = bit position of the first used data bit for a slot (within the data for each WS phase).
Page 449 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface MODE = 0; SCK_POL = 0; WS_POL = 0; MONO = 1. POSITiON = bit position of the first used data bit for slot 0 Left, bit position within the second half + 0x100 for Slot 0 Right.
Page 450 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface 27.7.2.3 I S signal polarities Figure 77 shows examples of SCK and WS polarities and how they relate to data positions. Fig 77. Data at the start of a frame, shown with both SCK and WS polarities 27.7.3 Data rates...
Page 451 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface The value of DIV would be (function clock divider input frequency / the required divider output frequency) - 1. If the divider input is 24.576 MHz (256 fs of the 96 kHz sample rate), the divider needs to divide by 4 (DIV = 3) to obtain the target divider output rate of 6.144...
Page 452 UM10914 NXP Semiconductors Chapter 27: LPC5411x I S interface – If a channel pair is configured with ONECHANNEL = 1, then only one value is transferred. 27.7.5 DMA The Flexcomm Interface can generate DMA requests based on FIFO levels. Data...
Page 453 UM10914 Chapter 28: LPC5411x DMIC subsystem Rev. 2.0 — 9 May 2018 User manual 28.1 How to read this chapter The DMIC subsystem, including the dual-channel digital PDM microphone interface (DMIC) and hardware voice activity detector (HWVAD), is available on all LPC5411x parts. 28.2 Features •...
Page 454 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem • PDM internal setup: – Enable DMIC PDM channels via the EN_CH0/1 bits in the CHANEN register. See Section 28.6.1. – Set up the internal clock dividers for the PDM channels used via the DIVHFCLK0/1 registers.
Page 455 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem 28.4 Pin description Table 476 gives a brief summary of each of the PDM pins used by the DMIC subsystem. Table 476. DMIC subsystem PDM pin description Type Description PDM0_CLK Clock output to digital microphone on PDM interface 0.
Page 456 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem CLK_BYPASS0 = 0; CLK_BYPASS1 = 0; DUAL_DATA = 0 Fig 79. Typical connection to two independent microphones CLK_BYPASS0 = 0; CLK_BYPASS1 = 0; DUAL_DATA = 1 Fig 80. Typical connection to two microphones sharing a data line CLK_BYPASS0 = 0;...
Page 457 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem CLK_BYPASS0 = 1 Fig 82. Bypass mode with an external device taking over microphone access 28.5 General description The hardware voice activity detector (HWVAD) implements a wave envelope detector and a floor noise envelope detector. It provides an interrupt when the delta between the two detectors is larger than a predefined value.
Page 458 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem 28.6 Register description Table 478. Register overview: DMIC subsystem (base address 0x4009 0000) Name Access Offset Description Reset value Section Registers for DMIC channel 0: OSR0 0x000 CIC filter decimation rate (oversample rate).
Page 459 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem 28.6.1 Oversample Rate register This register selects the oversample rate (CIC decimation rate) for the related input channel. Table 479. Oversample Rate register (OSR[0:1], offset 0x000 (OSR0) and 0x100 (OSR1)) bit description...
Page 460 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Fig 84. Pre-emphasis filter quantized response at 96 kHz 28.6.4 Pre-Emphasis Filter Coefficient for 4 FS register This register selects the pre-emphasis filter coefficient for the related input channel when 4 FS mode is used (see Section 28.6.13 “Use 2 FS...
Page 461 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Table 483. Decimator Gain Shift register (GAINSHFT[0:1], offset 0x010 (GAINSHFT0) and 0x110 (GAINSHFT1)) bit description Symbol Description Reset value GAIN Gain control, as a positive or negative (two’s complement) number of bits to shift.
Page 462 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Table 485. FIFO Status register (FIFOSTAT[0:1], offset 0x084 (FIFOSTAT0) and 0x184 (FIFOSTAT1)) bit description Symbol Description Reset value Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL register. Writing a one to this bit clears the flag.
Page 463 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Table 488. DC Control register (DCCTRL[0:1], offset 0x090 (DCCTRL0) and 0x190 (DCCTRL1)) bit description Symbol Value Description Reset value DCPOLE DC block filter. Flat response, no filter. 155 Hz. 78 Hz. 39 Hz.
Page 464 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Table 491. Use 2FS register (USE2FS, offset 0xF10) bit description Symbol Value Description Reset value USE2FS 0 Use 1FS output for PCM data. Use 2FS output for PCM data. 31:1 - Reserved. Read value is undefined, only zero should be written.
Page 465 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem 28.6.16 HWVAD control register This register controls the operation of the filter block and resets the internal interrupt flag. Once the HWVAD triggered an interrupt, a short ‘1’ pulse on bit ST10 clears the interrupt.
Page 466 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Table 497. HWVAD signal estimator gain register (HWVADTHGS, offset 0xF94) bit description Symbol Description Reset value THGS Gain value for the signal estimator. 0 to 14: 0 corresponds to a gain of 1.
Page 467 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem 28.7 Functional description 28.7.1 HWVAD The hardware voice activity detector (HWVAD) analyses the PCM data from DMIC channel 0 by means of a filter block. Both the noise floor and the signal wave are examined and result in separate filter outputs.
Page 468 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem With bit RSTT in register HWVADRSTT all filters can be reset. After this reset the HWVAD filters need to converge, so for the first few milliseconds the result is not reliable. The HWVAD interrupt should be masked on NVIV level during this time frame.
Page 469 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem 28.7.1.2.1 Input gain setting The 24-bit PCM input signal can be shifted left or right with the gain setting in the register HWVADGAIN. This increases or decreases the volume of the input signal for the HWVAD processing.
Page 470 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Fig 88. DMIC channel block diagram 28.7.2.1 Clocking and DMIC data rates The DMIC interface operation is determined by 3 clock domains: • DMIC interface base clock: supply clock for the peripheral block •...
Page 471 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem However, for power consumption reasons, it is preferable that the division to the required DMIC clock be done outside of the DMIC interface block (for example using register DMICCLKDIV in the SYSCON block).
Page 472 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem Fig 90. Principle structure of the PDM to PCM conversion To achieve lower power consumption, the DC filter can be supplied with the 2FS instead of the 1FS signal, bypassing the second half band decimator filter. This reduces the required DMIC base clock by a factor of 2.
Page 473 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem This also works when the device is in deep-sleep mode, as the FIFO event is able to wake up the required part of the hardware. After the DMA finished the job, the device will return into deep-sleep mode.
Page 474 UM10914 NXP Semiconductors Chapter 28: LPC5411x DMIC subsystem and issues an interrupt. With the DMA set to larger transfer sizes (maximum is 1024 transfers), there is quite some history data available for any type of software-based analysis of the data causing the HWVAD event.
Page 475 UM10914 Chapter 29: LPC5411x 12-bit ADC controller (ADC) Rev. 2.0 — 9 May 2018 User manual 29.1 How to read this chapter The ADC controller is available on all LPC5411x devices. The number of ADC channels available is dependent on the package size. 29.2 Features •...
Page 476 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) – Use the ADC clock, determined by the ADCCLKSEL register (Table 133) and the ADCCLKDIV register (Table 143). Some clock sources are independent of the system clock, and may require extra time to synchronize ADC trigger inputs.
Page 477 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.4 Pin description The ADC can measure the voltage on any of the input signals on the analog input channel. Digital signals must be disconnected from the ADC input pins when the ADC function is to be used by setting DIGIMODE = 0 on those pins in the related IOCON registers.
Page 478 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 502. ADC0 pin description Function Connect to Description ADC0_10 PIO1_7 Analog input channel 10. ADC0_11 PIO1_8 Analog input channel 11. ADC0_PINTRIG0 PINT0 ADC0 pin trigger input 0, from Pin Interrupt 0. Select in SEQA_CTRL or SEQB_CTRL.
Page 479 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.5 General description Fig 93. ADC block diagram The ADC controller provides a great deal of flexibility in launching and controlling sequences of ADC conversions using the associated 12-bit, successive approximation ADC converter.
Page 480 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6 Register description The reset value reflects the data stored in used bits only. It does not include reserved bits content. Table 504. Register overview: ADC (base address 0x400A 0000)
Page 481 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 504. Register overview: ADC (base address 0x400A 0000) Name Access Offset Description Reset Section value THR0_LOW 0x050 ADC Low Compare Threshold register 0: Contains the lower 29.6.8 threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
Page 482 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.1 ADC Control register This register specifies the clock divider value to be used to generate the ADC clock in synchronous mode and general operating mode bits including resolution and sampling time.
Page 483 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 505. ADC Control register (CTRL, offset 0x0) bit description Symbol Value Description Reset value BYPASSCAL Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application.
Page 484 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.3 ADC Conversion Sequence A Control register There are two independent conversion sequences that can be configured, each consisting of a set of conversions on one or more channels. This control register specifies the channel selection and trigger conditions for the A sequence and contains bits to allow software to initiate that conversion sequence.
Page 485 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 507: ADC Conversion Sequence A Control register (SEQA_CTRL, offset 0x08) bit description Symbol Value Description Reset value START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger.
Page 486 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 507: ADC Conversion Sequence A Control register (SEQA_CTRL, offset 0x08) bit description Symbol Value Description Reset value SEQA_ENA Sequence Enable. Remark: In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQA_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit).
Page 487 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.4 ADC Conversion Sequence B Control register There are two independent conversion sequences that can be configured, each consisting of a set of conversions on one or more channels. This control register specifies the channel selection and trigger conditions for the B sequence, as well bits to allow software to initiate that conversion sequence.
Page 488 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 508: ADC Conversion Sequence B Control register (SEQB_CTRL, offset 0x0C) bit description Symbol Value Description Reset value START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger.
Page 489 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Results of ADC conversions can be read in one of two ways. One is to use these ADC Global Data registers to read data from the ADC at the end of each ADC conversion.
Page 490 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 510: ADC Sequence B Global Data register (SEQB_GDAT, offset 0x14) bit description Symbol Description Reset value Reserved. 15:4 RESULT This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register.
Page 491 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.7 ADC Channel Data registers 0 to 11 The ADC Channel Data registers hold the result of the last conversion completed for each ADC channel. They also include status bits to indicate when a conversion has been completed, when a data overrun has occurred, and where the most recent conversion fits relative to the range dictated by the high and low threshold registers.
Page 492 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 511. ADC Data registers (DAT[0:11], offset [0x020:0x04C]) bit description Symbol Description Reset value 19:18 THCMPCROSS Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel.
Page 493 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.8 ADC Compare Low Threshold register 0 These registers set the LOW threshold levels against which ADC conversions on all channels will be compared. Each channel will either be compared to the THR0_LOW/HIGH registers or to the THR1_LOW/HIGH registers depending on what is specified for that channel in the CHAN_THRSEL register.
Page 494 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.10 ADC Compare High Threshold register 0 These registers set the HIGH threshold level against which ADC conversions on all channels will be compared. Each channel will either be compared to the THR0_LOW/HIGH registers or to the THR1_LOW/HIGH registers depending on what is specified for that channel in the CHAN_THRSEL register.
Page 495 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.12 ADC Channel Threshold Select register For each channel, this register indicates which pair of threshold registers conversion results should be compared to. Table 516: ADC Channel Threshold Select register (CHAN_THRSEL, offset 0x60) bit description...
Page 496 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.13 ADC Interrupt Enable register There are four separate interrupt requests generated by the ADC: conversion, these are -complete or sequence-complete interrupts for each of the two sequences, a threshold-comparison out-of-range interrupt, and a data overrun interrupt. The two conversion/sequence-complete interrupts can also serve as DMA triggers.
Page 497 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 517: ADC Interrupt Enable register (INTEN, offset 0x64) bit description Symbol Value Description Reset value ADCMPINTEN0 Threshold comparison interrupt enable for channel 0. Disabled. Outside threshold. Crossing threshold. Reserved ADCMPINTEN1 Channel 1 threshold comparison interrupt enable.
Page 498 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.14 ADC Flags register The ADC Flags registers contains the four interrupt/DMA trigger flags along with the individual overrun flags that contribute to an overrun interrupt and the component threshold-comparison flags that contribute to that interrupt. Note that the threshold and overrun interrupts hare a slot in the NVIC.
Page 499 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 518: ADC Flags register (FLAGS, offset 0x68) bit description Symbol Description Reset value SEQA_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A.
Page 500 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.6.15 ADC Startup register This register is used exclusively when enabling the ADC. This register should never be accessed during normal ADC operation. The ADC clock should be selected and running at full frequency prior to writing to this register.
Page 501 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.7 Functional description 29.7.1 Conversion Sequences A conversion sequence is a single pass through a series of ADC conversions performed on a selected set of ADC channels. Software can configure up to two independent conversion sequences, either of which can be triggered by software or by a transition on one of the hardware triggers.
Page 502 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.7.2.1 Avoiding spurious hardware triggers Care should be taken to avoid generating a spurious trigger when writing to the SEQn_CTRL register to change the trigger selected for the sequence, switch the polarity of the selected trigger, or to enable the sequence for operation.
Page 503 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) If the MODE bit for the sequence is 1 (sequence-complete mode) then the interrupt flag/DMA request must be written-to by software to clear it (except when used as a DMA trigger, in which case it will be cleared in hardware by the DMA engine).
Page 504 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.7.6 Offset calibration and enabling the ADC The A/D converter includes a built-in, self-calibration mode which can be used to minimize offset error. For applications where offset error is not a concern, calibration may be disabled by setting the BYPASSCAL bit in the CTRL register.
Page 505 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) The DMA transfer size determines when a DMA interrupt is generated. The transfer size can be set to the number of ADC channels being converted. Non-contiguous channels can be transferred by the DMA using the scatter/gather linked lists.
Page 506 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) Table 522. Minimum required sample times Selected ADC Analog signal Fast channels (ADC5:0) Slow channels (ADC11:6) Resolution source impedance Min. sample time TSAMP field Min. sample time TSAMP field 12 bits under 0.05k ohms...
Page 507 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.8 Examples 29.8.1 Perform a single ADC conversion triggered by software Remark: When ADC conversions are triggered by software only and hardware triggers are not used in the conversion sequence, follow these steps to avoid spurious conversions: 1.
Page 508 UM10914 NXP Semiconductors Chapter 29: LPC5411x 12-bit ADC controller (ADC) 29.8.2 Perform a sequence of conversions triggered by an external pin The ADC can perform conversions on a sequence of selected channels. Each individual conversion of the sequence (single-step) or the entire sequence can be triggered by hardware.
Page 509 UM10914 Chapter 30: LPC5411x Temperature sensor Rev. 2.0 — 9 May 2018 User manual 30.1 How to read this chapter The temperature sensor is available on all LPC5411x devices. 30.2 Features • Linear temperature sensor. • Sensor output internally connected to the ADC for temperature monitoring 30.3 Basic configuration •...
Page 510 UM10914 Chapter 31: LPC5411x CRC engine Rev. 2.0 — 9 May 2018 User manual 31.1 How to read this chapter The CRC engine is available on all LPC5411x parts. 31.2 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. –...
Page 511 UM10914 NXP Semiconductors Chapter 31: LPC5411x CRC engine 31.5 General description The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. Fig 94. CRC block diagram UM10914 All information provided in this document is subject to legal disclaimers.
Page 512 UM10914 NXP Semiconductors Chapter 31: LPC5411x CRC engine 31.6 Register description Table 523. Register overview: CRC engine (base address 0x4009 5000) Name Access Offset Description Reset value Section MODE 0x000 CRC mode register 31.6.1 SEED 0x004 CRC seed register 0xFFFF 31.6.2...
Page 513 UM10914 NXP Semiconductors Chapter 31: LPC5411x CRC engine 31.6.4 CRC data register This register is a Write-only register containing the data block for which the CRC sum will be calculated. Table 527. CRC data register (WR_DATA, offset 0x008) bit description...
Page 514 UM10914 NXP Semiconductors Chapter 31: LPC5411x CRC engine CRC-16 set-up Polynomial = x Seed Value = 0x0000 Bit order reverse for data input: YES 1's complement for data input: NO Bit order reverse for CRC sum: YES 1's complement for CRC sum: NO...
Page 515 UM10914 Chapter 32: LPC5411x Inter-CPU Mailbox Rev. 2.0 — 9 May 2018 User manual 32.1 How to read this chapter The Inter-CPU Mailbox is available on LPC5411x parts that include the Cortex M0+. 32.2 Features • Provides a means Inter-Processor Communication, allowing multiple CPUs to share resources and communicate with each other in a simple manner.
Page 516 UM10914 NXP Semiconductors Chapter 32: LPC5411x Inter-CPU Mailbox 32.6 Register description Table 528. Register overview: Mailbox (base address 0x4008 B000) Name Access Offset Description Reset value Section IRQ0 0x000 Interrupt request register for the Cortex-M0+ CPU. 32.6.1 IRQ0SET 0x004 Set bits in IRQ0 32.6.2...
Page 517 UM10914 NXP Semiconductors Chapter 32: LPC5411x Inter-CPU Mailbox 32.6.4 M4 interrupt register The IRQ1 register allows other CPUs to send interrupt requests to the Cortex-M4 CPU. This is intended to allow communication between CPUs. For example, one CPU could be handling certain peripherals and signalling another CPU when data is available Each bit can represent a different situation.
Page 518 UM10914 Chapter 33: LPC5411x Serial Wire Debug (SWD) Rev. 2.0 — 9 May 2018 User manual 33.1 How to read this chapter Debug functionality is available on all LPC5411x devices. Details depend on whether the Cortex-M0+ is present on the device. 33.2 Features •...
Page 519 UM10914 NXP Semiconductors Chapter 33: LPC5411x Serial Wire Debug (SWD) Table 536. Serial Wire Debug pin description Function Type Connect to Description SWCLK PIO0_16 Serial Wire Clock. This pin is the clock for SWD debug logic when in the Serial Wire Debug mode (SWD).
Page 520 UM10914 NXP Semiconductors Chapter 33: LPC5411x Serial Wire Debug (SWD) The debug mode changes the way in which reduced power modes work internal to the CPU. Therefore power measurements should not be made while debugging, power consumption is higher than during normal operation.
Page 521 UM10914 NXP Semiconductors Chapter 33: LPC5411x Serial Wire Debug (SWD) 33.6.3 Boundary scan The RESET pin selects between the test TAP controller for JTAG boundary scan (RESET = LOW) and the Arm SWD debug port TAP controller (RESET = HIGH). The Arm SWD debug port is disabled while the part is in reset.
Page 522 UM10914 NXP Semiconductors Chapter 33: LPC5411x Serial Wire Debug (SWD) Table 538. Register overview: ISP-AP (base address 0x4009 C000) Name Access Offset Description Reset value Section 0x000 Command and status word. 33.6.4.5.1 REQUEST 0x004 Request from the debugger to the device.
Page 523 UM10914 NXP Semiconductors Chapter 33: LPC5411x Serial Wire Debug (SWD) 33.6.4.6 ISP-AP commands Commands for the ISP-AP are listed below. These would be written to the REQUEST register. Table 543. ISP-AP commands Name Command Description code Enter ISP-AP Cause the device to enter ISP-AP command mode. This must be done prior to sending other commands.
Page 524 UM10914 Chapter 34: LPC5411x USB ROM API Rev. 2.0 — 9 May 2018 User manual 34.1 How to read this chapter The USB ROM driver routines are available on all LPC5411x devices. USB on-chip drivers are provided via the USB Stack in SDK and LPCOpen software packages. 34.2 Features •...
Page 525 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API and USBD_Core APIs. This module is designed to simplify the user code by exposing only the required interface needed to interface with Devices using the USB CDC-ACM Class. – Communication Device Class function driver initialization parameter data structure (Table 572 “USBD_CDC_INIT_PARAM class...
Page 526 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API – HID class API functions structure. This structure contains pointers to all the functions exposed by the HID function driver module (Table 578 “USBD_HW_API class structure”). • USB device controller driver –...
Page 527 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4 USB API 34.4.1 __WORD_BYTE Table 545. __WORD_BYTE class structure Member Description uint16_t __WORD_BYTE::W data member to do 16 bit access WB_TWB_T __WORD_BYTE::WB data member to do 8 bit access 34.4.2 _BM_T Table 546.
Page 528 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.5 _CDC_HEADER_DESCRIPTOR Table 549. _CDC_HEADER_DESCRIPTOR class structure Member Description bFunctionLength uint8_t _CDC_HEADER_DESCRIPTOR::bFunctionLength bDescriptorType uint8_t _CDC_HEADER_DESCRIPTOR::bDescriptorType bDescriptorSubtype uint8_t _CDC_HEADER_DESCRIPTOR::bDescriptorSubtype bcdCDC uint16_t _CDC_HEADER_DESCRIPTOR::bcdCDC 34.4.6 _CDC_LINE_CODING Table 550. _CDC_LINE_CODING class structure Member Description dwDTERate...
Page 529 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.10 _HID_DESCRIPTOR HID class-specific HID Descriptor. Table 554. _HID_DESCRIPTOR class structure Member Description bLength uint8_t _HID_DESCRIPTOR::bLength Size of the descriptor, in bytes. bDescriptorType uint8_t _HID_DESCRIPTOR::bDescriptorType Type of HID descriptor. bcdHID uint16_t _HID_DESCRIPTOR::bcdHID BCD encoded version that the HID descriptor and device complies to.
Page 530 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.13 _MSC_CBW Table 557. _MSC_CBW class structure Member Description dSignature uint32_t _MSC_CBW::dSignature dTag uint32_t _MSC_CBW::dTag dDataLength uint32_t _MSC_CBW::dDataLength bmFlags uint8_t _MSC_CBW::bmFlags bLUN uint8_t _MSC_CBW::bLUN bCBLength uint8_t _MSC_CBW::bCBLength uint8_t _MSC_CBW::CB[16][16] 34.4.14 _MSC_CSW Table 558.
Page 531 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.17 _USB_CORE_DESCS_T USB descriptors data structure. Table 561. _USB_CORE_DESCS_T class structure Member Description device_desc uint8_t * _USB_CORE_DESCS_T::device_desc Pointer to USB device descriptor string_desc uint8_t * _USB_CORE_DESCS_T::string_desc Pointer to array of USB string descriptors...
Page 532 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.19 _USB_DFU_FUNC_DESCRIPTOR Table 563. _USB_DFU_FUNC_DESCRIPTOR class structure Member Description bLength uint8_t _USB_DFU_FUNC_DESCRIPTOR::bLength bDescriptorType uint8_t _USB_DFU_FUNC_DESCRIPTOR::bDescriptorType bmAttributes uint8_t _USB_DFU_FUNC_DESCRIPTOR::bmAttributes wDetachTimeOut uint16_t _USB_DFU_FUNC_DESCRIPTOR::wDetachTimeOut wTransferSize uint16_t _USB_DFU_FUNC_DESCRIPTOR::wTransferSize bcdDFUVersion uint16_t _USB_DFU_FUNC_DESCRIPTOR::bcdDFUVersion 34.4.20 _USB_INTERFACE_DESCRIPTOR Table 564. _USB_INTERFACE_DESCRIPTOR class structure...
Page 533 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.21 _USB_OTHER_SPEED_CONFIGURATION Table 565. _USB_OTHER_SPEED_CONFIGURATION class structure Member Description bLength uint8_t _USB_OTHER_SPEED_CONFIGURATION::bLength Size of descriptor bDescriptorType uint8_t _USB_OTHER_SPEED_CONFIGURATION::bDescriptorType Other_speed_Configuration Type wTotalLength uint16_t _USB_OTHER_SPEED_CONFIGURATION::wTotalLength Total length of data returned bNumInterfaces uint8_t _USB_OTHER_SPEED_CONFIGURATION::bNumInterfaces...
Page 534 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.23 _USB_STRING_DESCRIPTOR Table 567. _USB_STRING_DESCRIPTOR class structure Member Description bLength uint8_t _USB_STRING_DESCRIPTOR::bLength Size of this descriptor in bytes bDescriptorType uint8_t _USB_STRING_DESCRIPTOR::bDescriptorType STRING Descriptor Type bString uint16_t _USB_STRING_DESCRIPTOR::bString UNICODE encoded string 34.4.24 _WB_T Table 568.
Page 535 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 569. USBD_API class structure Member Description const USBD_CDC_API_T* USBD_API::cdc Pointer to function table which exposes functions provided by CDC-ACM function driver module. reserved6 const uint32_t* USBD_API::reserved6 Reserved for future function driver module.
Page 536 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 570. USBD_API_INIT_PARAM class structure Member Description USB_Resume_Event USB_CB_T USBD_API_INIT_PARAM::USB_Resume_Event Event for USB wake up or resume. This event fires when a the USB device interface is suspended and the host wakes up the device by supplying Start Of Frame pulses. This is generally hooked to pull the user application out of a low power state and back into normal operating mode.
Page 537 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 570. USBD_API_INIT_PARAM class structure Member Description USB_Configure_Event USB_CB_T USBD_API_INIT_PARAM::USB_Configure_Event Event for USB configuration number changed. This event fires when a the USB host changes the selected configuration number. On receiving configuration change request from host, the stack enables/configures the endpoints needed by the new configuration before calling this callback function.
Page 538 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 571. USBD_CDC_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_CDC_API::init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T *param, USBD_HANDLE_T *phCDC) Function to initialize CDC function driver module. This function is called by application layer to initialize CDC function driver module.
Page 539 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.28 USBD_CDC_INIT_PARAM Communication Device Class function driver initialization parameter data structure. Table 572. USBD_CDC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_CDC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers.
Page 540 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 572. USBD_CDC_INIT_PARAM class structure Member Description CIC_SetRequest ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t length) Communication Interface Class specific set request call-back function. This function is provided by the application software. This function gets called when host sends a CIC management element requests.
Page 541 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 572. USBD_CDC_INIT_PARAM class structure Member Description CDC_BulkOUT_Hdlr ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkOUT_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event) Communication Device Class specific BULK OUT endpoint handler. The application software should provide the BULK OUT endpoint handler. Applications should transfer data depending on the communication protocol type set in descriptors.
Page 542 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 572. USBD_CDC_INIT_PARAM class structure Member Description SetCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature, uint8_t *buffer, uint16_t len) Abstract control model(ACM) subclass specific SET_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a SET_COMM_FEATURE set request.
Page 543 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 572. USBD_CDC_INIT_PARAM class structure Member Description ClrCommFeature ErrorCode_t(* USBD_CDC_INIT_PARAM::ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature) Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function. This function is provided by the application software. This function gets called when host sends a CLEAR_COMM_FEATURE request.
Page 544 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 572. USBD_CDC_INIT_PARAM class structure Member Description SetLineCode ErrorCode_t(* USBD_CDC_INIT_PARAM::SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING *line_coding) Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function. This function is provided by the application software. This function gets called when host sends a SET_LINE_CODING request.
Page 545 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.29 USBD_CORE_API USBD stack Core API functions structure. Table 573. USBD_CORE_API class structure Member Description RegisterClassHandler ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterClassHandler)(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void *data) Function to register class specific EP0 event handler with USB device stack.
Page 546 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 573. USBD_CORE_API class structure Member Description SetupStage void(*void USBD_CORE_API::SetupStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in setup state. This function is called by USB stack and the application layer to set the EP0 state machine in setup state.
Page 547 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 573. USBD_CORE_API class structure Member Description StatusOutStage void(*void USBD_CORE_API::StatusOutStage)(USBD_HANDLE_T hUsb) Function to set EP0 state machine in status_out state. This function is called by USB stack and the application layer to set the EP0 state machine in status_out state.
Page 548 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 574. USBD_DFU_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_DFU_API::init)(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T *param, uint32_t init_state) Function to initialize DFU function driver module. This function is called by application layer to initialize DFU function driver module.
Page 549 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 575. USBD_DFU_INIT_PARAM class structure Member Description DFU_Write uint8_t(*uint8_t(* USBD_DFU_INIT_PARAM::DFU_Write)(uint32_t block_num, uint8_t **src, uint32_t length, uint8_t *bwPollTimeout))(uint32_t block_num, uint8_t **src, uint32_t length, uint8_t *bwPollTimeout) DFU Write callback function. This function is provided by the application software. This function gets called when host sends a write command.
Page 550 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 575. USBD_DFU_INIT_PARAM class structure Member Description DFU_Ep0_Hdlr ErrorCode_t(* USBD_DFU_INIT_PARAM::DFU_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default DFU class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 551 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 576. USBD_HID_API class structure Member Description init ErrorCode_t(*ErrorCode_t USBD_HID_API::init)(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T *param) Function to initialize HID function driver module. This function is called by application layer to initialize HID function driver module. On successful initialization the function returns a handle to HID function driver module in passed param structure.
Page 552 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 577. USBD_HID_INIT_PARAM class structure Member Description HID_GetReport ErrorCode_t(* USBD_HID_INIT_PARAM::HID_GetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuffer, uint16_t *length) HID get report callback function. This function is provided by the application software. This function gets called when host sends a HID_REQUEST_GET_REPORT request.
Page 553 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 577. USBD_HID_INIT_PARAM class structure Member Description HID_GetPhysDesc ErrorCode_t(* USBD_HID_INIT_PARAM::HID_GetPhysDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t **pBuf, uint16_t *length) Optional callback function to handle HID_GetPhysDesc request. The application software could provide this callback HID_GetPhysDesc handler to handle get physical descriptor requests sent by the host.
Page 554 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 577. USBD_HID_INIT_PARAM class structure Member Description HID_SetProtocol ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetProtocol)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup, uint8_t protocol) Optional callback function to handle HID_REQUEST_SET_PROTOCOL request. The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL requests sent by the host.
Page 555 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 577. USBD_HID_INIT_PARAM class structure Member Description HID_EpOut_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpOut_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional Interrupt OUT endpoint event handler. The application software could provide Interrupt OUT endpoint event handler. Application which receives reports from host on interrupt endpoint should provide an endpoint event handler through this data member.
Page 556 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 577. USBD_HID_INIT_PARAM class structure Member Description HID_Ep0_Hdlr ErrorCode_t(* USBD_HID_INIT_PARAM::HID_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default HID class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 557 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 578. USBD_HW_API class structure Member Description Connect void(*void USBD_HW_API::Connect)(USBD_HANDLE_T hUsb, uint32_t con) Function to make USB device visible/invisible on the USB bus. This function is called after the USB initialization. This function uses the soft connect feature to make the device visible on the USB bus.
Page 558 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 578. USBD_HW_API class structure Member Description WakeUpCfg void(*void USBD_HW_API::WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg) Function to configure USB device controller to walk-up host on remote events. This function is called by application layer to configure the USB device controller to wake up on remote events.
Page 559 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 578. USBD_HW_API class structure Member Description ConfigEP void(*void USBD_HW_API::ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD) Function to configure USB Endpoint according to descriptor. This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received by the stack from USB host.
Page 560 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 578. USBD_HW_API class structure Member Description DisableEP void(*void USBD_HW_API::DisableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum) Function to disable selected USB endpoint. This function disables interrupts on selected endpoint. Parameters: 1. hUsb = Handle to the USB device stack.
Page 561 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 578. USBD_HW_API class structure Member Description ReadEP uint32_t(*uint32_t USBD_HW_API::ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData) Function to read data received on the requested endpoint. This function is called by USB stack and the application layer to read the data received on the requested endpoint.
Page 562 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 578. USBD_HW_API class structure Member Description WakeUp void(*void USBD_HW_API::WakeUp)(USBD_HANDLE_T hUsb) Function to generate resume signaling on bus for remote host wake-up. This function is called by application layer to remotely wake up host controller when system is in suspend state.
Page 563 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API 34.4.36 USBD_MSC_INIT_PARAM Mass Storage class function driver initialization parameter data structure. Table 580. USBD_MSC_INIT_PARAM class structure Member Description mem_base uint32_t USBD_MSC_INIT_PARAM::mem_base Base memory location from where the stack can allocate data and buffers.
Page 564 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 580. USBD_MSC_INIT_PARAM class structure Member Description MSC_Read void(*void(* USBD_MSC_INIT_PARAM::MSC_Read)(uint32_t offset, uint8_t **dst, uint32_t length))(uint32_t offset, uint8_t **dst, uint32_t length) MSC Read callback function. This function is provided by the application software. This function gets called when host sends a read command.
Page 565 UM10914 NXP Semiconductors Chapter 34: LPC5411x USB ROM API Table 580. USBD_MSC_INIT_PARAM class structure Member Description MSC_Ep0_Hdlr ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event) Optional user overridable function to replace the default MSC class handler. The application software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure.
Page 566 UM10914 Chapter 35: LPC5411x Flash signature generator Rev. 2.0 — 9 May 2018 User manual 35.1 How to read this chapter The flash signature generator is present on all LPC5411x devices. 35.2 Features • Controls hardware flash signature generation. • Signature generated for the entire flash or for a specified address range.
Page 567 UM10914 NXP Semiconductors Chapter 35: LPC5411x Flash signature generator 35.4 Register description Remark: To configure flash access times, use the FLASHCFG register in the SYSCON block. See Section 6.5.41. Table 581. Register overview: FMC (base address 0x4003 4000) Name Access Offset Description...
Page 568 UM10914 NXP Semiconductors Chapter 35: LPC5411x Flash signature generator and the stop address to the signature stop address register (FMSSTOP. The start and stop addresses must be aligned to 128-bit boundaries and can be derived by dividing the byte address by 16.
Page 569 UM10914 NXP Semiconductors Chapter 35: LPC5411x Flash signature generator 35.4.5 Signature status register The read-only FMSTAT register provides a means of determining when signature generation has completed. Completion of signature generation can be checked by polling the SIG_DONE bit in FMSTAT. SIG_DONE should be cleared via the FMSTATCLR register before starting a signature generation operation, otherwise the status might indicate completion of a previous operation.
Page 570 UM10914 NXP Semiconductors Chapter 35: LPC5411x Flash signature generator 35.5 Functional description 35.5.1 Algorithm and procedure for signature generation 35.5.1.1 Signature generation A signature can be generated for any part of the flash contents. The address range to be used for signature generation is defined by writing the start address to the FMSSTART register, and the stop address to the FMSSTOP register.
Page 571 UM10914 Chapter 36: Arm Cortex Appendix Rev. 2.0 — 9 May 2018 User manual 36.1 Arm Cortex-M4 Details Arm Limited publishes the document “Cortex™-M4 Devices Generic User Guide”, which is available on their website at: • For the online manual, go to “developer.arm.com”, then search for “cortex-m4 devices generic user guide”.
Page 572 UM10914 NXP Semiconductors Chapter 36: Arm Cortex Appendix 36.2 Arm Cortex-M0+ Details (present on selected devices) Arm Limited publishes the document “Cortex™-M0+ Devices Generic User Guide”, which is available on their website at: • For the online manual, go to “developer.arm.com”, then search for “cortex-mo+ devices generic user guide”.
Page 573 UM10914 Chapter 37: Supplementary information Rev. 2.0 — 9 May 2018 User manual 37.1 Abbreviations Table 592. Abbreviations Acronym Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus Application Programming Interface BrownOut Detection Boot At power-up or chip reset, any method of importing code from an external source to execute from on-chip SRAM, or code executed in place from the external memory.
Page 574 UM10914 NXP Semiconductors Chapter 37: Supplementary information Cortex-M0+ TRM — Arm Cortex-M0+ Processor Technical Reference Manual AN11538 — AN11538 application note and code bundle (SCT cookbook) UM10204 — I C-bus specification and user manual UM10914 All information provided in this document is subject to legal disclaimers.
Page 575 In no event shall NXP Semiconductors, its affiliates or their suppliers be liable use of such information. to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business 37.3.2 Disclaimers...
Page 576 UM10914 NXP Semiconductors Chapter 37: Supplementary information 37.4 Tables Table 1. SRAM configuration .....14 Table 51. Command packet ..... . . 56 Table 2.
Page 577 UM10914 NXP Semiconductors Chapter 37: Supplementary information (base address 0x4000 0000) ....83 Table 128. Clock control clear register 1 Table 106. Register overview: Asynchronous system (AHBCLKCTRLCLR1, main syscon: offset 0x244) configuration (base address 0x4004 0000) .
Page 578 UM10914 NXP Semiconductors Chapter 37: Supplementary information description ......104 description ......120 Table 152.
Page 579 UM10914 NXP Semiconductors Chapter 37: Supplementary information pin functions for port 0 ....157 register (IENR, offset 0x004) bit description . 185 Table 208. Type D I/O Control registers: FUNC values and Table 237.
Page 580 UM10914 NXP Semiconductors Chapter 37: Supplementary information offset 0x020) bit description ....218 offset 0x04C) bit description ... . . 248 Table 266.
Page 581 UM10914 NXP Semiconductors Chapter 37: Supplementary information description ......272 Table 349. Module Configuration register (MODCFG, offset Table 320.
Page 582 UM10914 NXP Semiconductors Chapter 37: Supplementary information Table 380: Flexcomm Interface Pin Description ..338 description ......374 Table 381: Flexcomm Interface base addresses and Table 411.
Page 583 UM10914 NXP Semiconductors Chapter 37: Supplementary information Table 443. I C Interrupt Status register (INTSTAT, offset Table 473. FIFO data read with no FIFO pop 0x818) bit description ....413 (FIFORDNOPOP - offset 0xE40) bit description .
Page 584 UM10914 NXP Semiconductors Chapter 37: Supplementary information Table 495. HWVAD filter reset register (HWVADRSTT, offset Table 529. M0+ interrupt register (IRQ0, offset 0x000) bit 0xF8C) bit description....465 description .
Page 585 UM10914 NXP Semiconductors Chapter 37: Supplementary information Table 564. _USB_INTERFACE_DESCRIPTOR class structure ......532 Table 565.
Page 586 UM10914 NXP Semiconductors Chapter 37: Supplementary information 37.5 Figures Fig 1. Block diagram ......12 Fig 45.
Page 587 UM10914 NXP Semiconductors Chapter 37: Supplementary information Fig 92. ADC clocking ......476 Fig 93. ADC block diagram ..... .479 Fig 94.
Page 588 UM10914 NXP Semiconductors Chapter 37: Supplementary information 37.6 Contents Chapter 1: LPC5411x Introductory information Introduction ......8 Architectural overview .
Page 589 UM10914 NXP Semiconductors Chapter 37: Supplementary information 4.6.8 Reinvoke ISP ......48 4.8.4 SH_CMD_CHECK_IMAGE (0xA4) command 55 4.6.9...
Page 590 UM10914 NXP Semiconductors Chapter 37: Supplementary information 6.5.28 Flexcomm Interface clock source select registers 6.5.59 Start enable clear register 1 ....117 6.5.60 Hardware Wake-up control register ..118 6.5.29...
Page 591 UM10914 NXP Semiconductors Chapter 37: Supplementary information 7.3.4 Deep-sleep mode ..... 141 7.3.5.2 Wake-up from deep power-down mode: . . . 143 7.3.4.1...
Page 592 UM10914 NXP Semiconductors Chapter 37: Supplementary information 11.5.7 GPIO port set registers ....173 11.6 Functional description ....176 11.5.8...
Page 593 UM10914 NXP Semiconductors Chapter 37: Supplementary information 14.6.18 Channel transfer configuration registers . . . 226 Chapter 15: LPC5411x SCTimer/PWM (SCT) 15.1 How to read this chapter ....228 15.6.16...
Page 594 UM10914 NXP Semiconductors Chapter 37: Supplementary information Chapter 17: LPC5411x Windowed Watchdog Timer (WWDT) 17.1 How to read this chapter ....282 17.5.3.2 Changing the WWDT reload value ..286 17.2...
Page 595 UM10914 NXP Semiconductors Chapter 37: Supplementary information 22.5 General description ....316 22.6.10 USB interrupt enable register... . 327 22.6.11...
Page 596 UM10914 NXP Semiconductors Chapter 37: Supplementary information Chapter 25: LPC5411x Serial Peripheral Interfaces (SPI) 25.1 How to read this chapter ....369 25.6.11 FIFO interrupt enable set and read ..383 25.6.12...
Page 597 UM10914 NXP Semiconductors Chapter 37: Supplementary information 27.4 General description ....430 27.6.15 FIFO data read with no FIFO pop ..444 27.6.16...
Page 598 UM10914 NXP Semiconductors Chapter 37: Supplementary information 29.6.15 ADC Startup register....500 29.7.5 Optional Operating Modes ....503 29.6.16...
Page 599 UM10914 NXP Semiconductors Chapter 37: Supplementary information Chapter 34: LPC5411x USB ROM API 34.1 How to read this chapter ....524 34.4.14 _MSC_CSW......530 34.4.15...
Page 600 UM10914 NXP Semiconductors Chapter 37: Supplementary information Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com...