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Alinx AX530 User Manual

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Cyclone IV FPGA
Development Board
AX530
User Manual

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  • Page 1 Cyclone IV FPGA Development Board AX530 User Manual...
  • Page 2 Cyclone IV FPGA Development Board AX530 User Manual Version Record Version Date Release By Description Rev 1.0 2019-04-30 Rachel Zhou First Release 2 / 53 www.alinx.com...

  • Page 3: Table Of Contents

    Cyclone IV FPGA Development Board AX530 User Manual Table of Contents Part 1: FPGA Development Board Introduction..........5 Part 2: Structure Diagram..................8 Part 3: Power......................9 Part 4: FPGA Chip....................11 Part 4.1: FPGA resources.............12 Part 4.2: JTAG Interface............13 Part 4.3: FPGA Power Supply..........14 Part 5: 50Mhz Clock.....................15...
  • Page 4 Cyclone IV FPGA Development Board AX530 User Manual Part 20: 7-segment displays................51 4 / 53 www.alinx.com...

  • Page 5: Part 1: Fpga Development Board Introduction

    Cyclone IV FPGA Development Board AX530 User Manual The FPGA development board (AX530) is an entry-level product, mainly for FPGA beginners. The FPGA development board uses the ALTERA CYCLONE IV family chips, model EP4CE30F23C8, in a 484-pin FBGA package. The AX530 FPGA development board has a wealth of hardware resources and peripheral interfaces.
  • Page 6 Maximum User I/O Table 1-1: The Main Resources and Feature of ALTERA EP4CE30 The layout of the board that indicates the location of the connector and key components, provide a quickly overview of AX530 board (see Figure 1-2) 6 / 53 www.alinx.com...
  • Page 7 Cyclone IV FPGA Development Board AX530 User Manual Figure 1-2: The Layout of the AX530 Through this diagram, we can see the functions that the development platform can achieve.  +5V power input, maximum 2A current protection  A large-capacity 2Gbit high-speed DDR2 SDRAM can be used as a data cache or as a memory for NIOS II operation;...

  • Page 8: Part 2: Structure Diagram

     On-board 50M active crystal oscillator provides stable clock source for FPGA development board  3-Way 40-pin ALINX expansion port (0.1 inch), each expansion port with 34 IO ports, one 5V power supply, two 3.3V power supplies, three GND. Two expansion modules can be connected at the same time, such as expansion modules such as 4.3-inch TFT module and AD/DA module.

  • Page 9: Part 3: Power

    FPGA board for fixing the development board. The hole diameter of the positioning hole are 3.3mm (diameter) Figure 2-1: Structure Diagram Part 3: Power The power supply voltage of the AX530 FPGA development board is DC5V, and Figure 3-1 is the power supply schematic: 9 / 53 www.alinx.com...
  • Page 10 Cyclone IV FPGA Development Board AX530 User Manual Figure 3-1: Block Diagram of Power Design The FPGA development board is powered by +5V, and is converted into +3.3V, +1.2V, +1.8V three-way power supply through three-way DC/DC power supply chip MP1482, and generates +2.5V power supply and VCCIO (2.5V) through two LDO LT1117.

  • Page 11: Part 4: Fpga Chip

    Cyclone IV FPGA Development Board AX530 User Manual The IO voltage of FPGA BANK7 can be selected by two 0 ohm resistors (R158, R159) on the FPGA development board. When R158 is installed and R159 is not installed, the IO level of Bank7 is 3.3V. When R158 is not installed, R159 is installed.

  • Page 12: Part 4.1: Fpga Resources

    The EP4CE30F23C8 chip contains logic resources, built-in RAM, multiplier, phase-locked loop, global clock network and IO port. The resources between different types of FPGAs will be different. The resources of the FPGA model on the AX530 development board are shown in Figure 4-2 below 12 / 53 www.alinx.com...

  • Page 13: Part 4.2: Jtag Interface

    Cyclone IV FPGA Development Board AX530 User Manual Figure 4-2：FPGA internal resources Part 4.2: JTAG Interface First let's talk about the FPGA configuration and debugging interface: JTAG interface. The function of the JTAG interface is to download the compiled program (.sof) to the FPGA or download the configuration file (.jic) to the configuration chip EPCS64.

  • Page 14: Part 4.3: Fpga Power Supply

    Cyclone IV FPGA Development Board AX530 User Manual The JTAG interface uses a 10-pin 2.54mm standard connector, and Figure 4-4 shows the JTAG interface on the FPGA development board. Figure 4-4: JTAG Connector on the FPGA board Part 4.3: FPGA Power Supply...

  • Page 15: Part 5: 50Mhz Clock

    Cyclone IV FPGA Development Board AX530 User Manual Figure 4-5: FPGA Power Supply Part 5: 50Mhz Clock Figure 5-1 is the 50M active crystal oscillator circuit mentioned above that provides the clock source for the FPGA development board. The crystal output is connected to the global clock (GCLK Pin T21) of the FPGA, which can be used to drive the user logic within the FPGA.

  • Page 16: Part 6: Spi Flash Configuration Chip

    Cyclone IV FPGA Development Board AX530 User Manual Figure 5-2: 50Mhz crystal oscillator on the FPGA Development Board Clock Pin Assignment Net Name FPGA PIN Part 6: SPI Flash Configuration chip A 64Mbit configuration chip is used on the development board, the model is M25P64.
  • Page 17 Cyclone IV FPGA Development Board AX530 User Manual Part Device Size Manufacturer M25P16VMF 64M bit Table 6-1: The model of SPI Flash and Parameters Figure 6-1: The Hardware Design of SPI FLASH Figure 6-2: EPCS64(M25P64) on the FPGA board Configure chip pin assignments:...

  • Page 18: Part 7: Qspi Flash

    Cyclone IV FPGA Development Board AX530 User Manual Part 7: QSPI Flash The AX530 FPGA development board is equipped with a 128MBit Quad-SPI FLASH chip, model W25Q128, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, In use, QSPI FLASH can be used as power-down storage for user data.

  • Page 19: Part 8: Ddr2 Dram

    Cyclone IV FPGA Development Board AX530 User Manual Figure 7-2: QSPI Flash chip on the FPGA board Configure chip pin assignments: Pin Name FPGA Pin QSPI_CLK QSPI_CS QSPI_MISO0 QSPI_MISO1 QSPI_MISO2 QSPI_MISO3 Part 8: DDR2 DRAM The development board contains a high-speed DDR2 DRAM, model: MT47H128M16HR-3IT, capacity: 2Gbit (128M*16bit), 16bit bus.
  • Page 20 Cyclone IV FPGA Development Board AX530 User Manual DDR2 is up to 166.7MHz, and the data frequency is up to 333MHz. The hardware design of DDR2 requires strict consideration of signal integrity. In the circuit design and PCB design, the matching resistor/terminal resistor, trace impedance control, and trace length control have been fully considered to ensure the high-speed stability of DDR2.
  • Page 21 Cyclone IV FPGA Development Board AX530 User Manual DDR2 DRAM Pin Assignment: Pin Name FPGA Pin DDR2_DQS[0] DDR2_DQS[1] DDR2_DQ[0] DDR2_DQ [1] DDR2_DQ [2] DDR2_DQ [3] DDR2_DQ [4] DDR2_DQ [5] DDR2_DQ [6] DDR2_DQ [7] DDR2_DQ [8] DDR2_DQ [9] DDR2_DQ [10] DDR2_DQ [11]...

  • Page 22: Part 9: Eeprom 24Lc04

    Cyclone IV FPGA Development Board AX530 User Manual DDR2_A [11] DDR2_A [12] DDR2_A [13] DDR2_A [14] DDR2_BA [0] DDR2_BA [1] DDR2_BA [2] DDR2_RAS_N DDR2_CAS_N AB10 DDR2_WE_N DDR2_ODT DDR2_CLK AA17 DDR2_CLK_N AB17 DDR2_CKE DDR2_CS_N Part 9: EEPROM 24LC04 The development board contains an EEPROM, model 24LC04, and its capacity is 4Kbit (2*256*8bit).

  • Page 23: Part 10:Real-Time Clock

    Cyclone IV FPGA Development Board AX530 User Manual Figure 9-1: EEPROM Design Figure 9-2: EEPROM on the AX515 FPGA board EEPROM PIN assignment: Net Name FPGA PIN EEPROM_I2C_SDA EEPROM_I2C_SCL Part 10:Real-Time Clock The FPGA development board contains a real-time clock RTC chip, model 23 / 53 www.alinx.com...
  • Page 24 Cyclone IV FPGA Development Board AX530 User Manual DS1302. Its function is to provide the calendar function to 2099, with days, minutes, minutes, seconds and weeks. If time is required in the system, the RTC needs to be designed into the product. He needs to connect a 32.768KHz passive clock to provide an accurate clock source to the clock chip, so that the RTC can accurately provide clock information to the product.

  • Page 25: Part 11: Gigabit Ethernet Interface

    Cyclone IV FPGA Development Board AX530 User Manual Figure 10-2: DS1302 Circuit on FPGA board DS1302 Interface Pin Assignment： Net Name FPGA PIN RTC_SIO RTC_RESET RTC_SCLK Part 11: Gigabit Ethernet Interface The AX530 FPGA development board provides network communication services to users through the Realtek RTL8211EG Ethernet PHY chip. The RTL8211EG chip supports 10/100/1000 Mbps network transmission rate and communicates with the FPGA through the GMII interface.
  • Page 26 Cyclone IV FPGA Development Board AX530 User Manual Configuration Pin Instructions Configuration value PHYAD[2:0] MDIO/MDC Mode PHY Address PHY Address 011 3.3V, 2.5V, 1.5/1.8V voltage SELRGV 3.3V selection AN[1:0] Auto-negotiation configuration (10/100/1000M) adaptive RX Delay Delay RX clock 2ns delay...
  • Page 27 Cyclone IV FPGA Development Board AX530 User Manual Figure 11-2: Ethernet PHY chip on the FPGA board Gigabit Ethernet pin assignments are as follows： Signal Name FPGA Pin Description E_GCLK Ethernet GMII transmit clock E_TXD0 Ethernet Transmit Data bit0 E_TXD1...

  • Page 28: Part 12: Usb To Serial Port

    Ethernet Management Data Part 12: USB to Serial Port The AX530 FPGA development board includes the USB-UAR chip of Silicon Labs CP2102GM. The USB interface uses the MINI USB interface. It can be connected to the USB port of the upper PC for serial data communication with a USB cable.
  • Page 29 Cyclone IV FPGA Development Board AX530 User Manual Figure 12-2: USB to Serial Port on the FPGA Board At the same time, two LED indicators LED7 (RXD) and LED8 (TXD) are set for the serial port signal, and the silkscreen on the PCB is TX and RX, indicating...

  • Page 30: Part 13: Vga Port

    Cyclone IV FPGA Development Board AX530 User Manual Figure 12-4: USB to Serial Port LED Indicator on FPGA Board Serial Port Pin Assignment Pin Name FPGA Pin UART_RXD UART_TXD Part 13: VGA Port VGA interface, I believe many friends will not be unfamiliar, because this interface is the most important interface on the computer monitor.
  • Page 31 Cyclone IV FPGA Development Board AX530 User Manual Figure 13-1: VGA video signal transmission diagram HSYNC and VSYNC are line data synchronization and frame data synchronization, respectively, which are TTL levels. The FPGA can only output digital signals, while the R, G, and B required by VGA are analog signals. The digital to analog signal of VGA is realized by a simple resistor circuit.
  • Page 32 Cyclone IV FPGA Development Board AX530 User Manual Figure 13-3: VGA Interface on board VGA Interface Pin Assignment Pin Name FPGA Pin Description VGA_B[0] BLUE[0] VGA_B[1] BLUE[1] VGA_B[2] BLUE[2] VGA_B[3] BLUE[3] VGA_B[4] BLUE[4] VGA_G[0] GREEN[0] VGA_G[1] GREEN[1] VGA_G[2] GREEN[2] VGA_G[3]...

  • Page 33: Part 14: Usb 2.0 Interface

    Cyclone IV FPGA Development Board AX530 User Manual Part 14: USB 2.0 interface The FPGA development board uses Cypress CY7C68013A USB2.0 controller chip to realize high-speed data communication between PC and FPGA. CY7C68013A controller fully complies with the universal serial bus protocol version 2.0 specifications, supports full speed (12Mbit/s) and low...
  • Page 34 Cyclone IV FPGA Development Board AX530 User Manual Figure 14-1: FPGA and CY7C68013A connection diagram Figure 14-2 is a USB2.0 interface schematic, U12 is CY7C68013A, J10 is a USB interface. Figure 14-2: USB2.0 interface on the FPGA Board 34 / 53...
  • Page 35 Cyclone IV FPGA Development Board AX530 User Manual USB2.0 Pin Assignment： Pin Name FPGA Pin Description USB_CLKOUT 12-, 24- or 48 MHz clock output USB_IFCLK Synchronous Communication Clock Signal USB_FLAGA Status Output Signal USB_FLAGB Status Output Signal USB_FLAGC Status Output Signal...

  • Page 36: Part 15: Audio Interface

    Cyclone IV FPGA Development Board AX530 User Manual Part 15: Audio Interface The AX530 FPGA development board uses the Wolfon WM8731 audio codec (CODEC) chip to provide users with a high-quality audio interface. The chip supports microphone input, line input and line output port, and the sampling rate is adjustable from 8kHz to 96kHz.

  • Page 37: Part 16: Sd Card Slot

    Cyclone IV FPGA Development Board AX530 User Manual Figure 15-2: Audio interface on the FPGA board Audio WM8731 Pin Assignment: Pin Name FPGA Pin Description VM_I2C_SCLK WM8731 IIC Clock VM_I2C_SDAT WM8731 IIC Clock VM_BCLK Audio data clock signal Audio data output...
  • Page 38 Cyclone IV FPGA Development Board AX530 User Manual the United States conducted substantial research and development. In 2000, these companies initiated the establishment of the SD Association (Secure Digital Association, SDA), which has a strong lineup and attracted a large number of manufacturers.

  • Page 39: Part 17: Expansion Header

    SD_DAT2 SD_DAT3 Part 17: Expansion Header The AX530 FPGA development board is reserved with three 0.1inch spacing standard 40-pin expansion headers J1, J2, J3. Each expansion header has 40 signals, of which 1-channel 5V power supply, 2-channel3.3 V power 39 / 53...

  • Page 40: Part 17.1: Expansion Header J1

    Cyclone IV FPGA Development Board AX530 User Manual supply, 3-channle ground and 34 IOs. Do not directly connect the IO directly to the 5V device to avoid burning the FPGA. If you want to connect 5V equipment, you need to connect level conversion chip.
  • Page 41 Cyclone IV FPGA Development Board AX530 User Manual Figure 17-2: Expansion header J1 on the FPGA Board J1 Expansion Header Pin Assignment Pin Number FPGA Pin Pin Number FPGA Pin VCC5V 41 / 53 www.alinx.com...

  • Page 42: Part 17.2: Expansion Header J2

    Cyclone IV FPGA Development Board AX530 User Manual VCC3V3 VCC3V3 Part 17.2: Expansion header J2 Figure 17-3 shows the J1 expansion port connection diagram. Pin1, Pin37, Pin38 are GND, Pin2 is +5V, and Pin39 and Pin40 are +3.3V. Figure 17-3 shows the J2 expansion port connection diagram. Pin1, Pin37, Pin38 are GND, Pin2 is +5V, and Pin39 and Pin40 are +3.3V.
  • Page 43 Cyclone IV FPGA Development Board AX530 User Manual Figure 17-3: Expansion header J2 schematic Figure 17-4 shows the differential trace of the J2 expansion port PCB. The differential line implements strict isometric, equidistant and impedance 100 ohm control. 43 / 53...
  • Page 44 Cyclone IV FPGA Development Board AX530 User Manual Figure 17-4: J2 expansion port PCB trace The IO port of the J2 expansion port is connected FPGA Bank7, and the default level is 3.3V. If the user needs to modify IO of J2 to 2.5V level, you can adjust the 0 ohm resistor on the board (R158 is not installed, R159 is installed).
  • Page 45 Cyclone IV FPGA Development Board AX530 User Manual Figure 17-5: Power supply of J2 expansion port Figure 17-6: J2 expansion port on the FPGA Board 45 / 53 www.alinx.com...
  • Page 46 Cyclone IV FPGA Development Board AX530 User Manual J2 Expansion Header Pin Assignment Pin Number FPGA Pin Pin Number FPGA Pin VCC5V VCC3V3 VCC3V3 46 / 53 www.alinx.com...

  • Page 47: Part 17.3: Expansion Header J3

    Cyclone IV FPGA Development Board AX530 User Manual Part 17.3: Expansion header J3 Figure 17-7: Expansion header J3 schematic Figure 17-8: Expansion header J3 on the FPGA Board 47 / 53 www.alinx.com...

  • Page 48: Part 18: Led

    VCC3V3 Part 18: LED There are six red LEDs on the AX530 FPGA development board, one of which is the power indicator (PWR), four are users LED lights (LED1~LED4). The schematic of the four user LED sections is shown in Figure 18-1. When the FPGA pin output is logic 0, the LED will go out.

  • Page 49: Part 19: Buttons

    Figure 18-1: User LEDs Schematic Figure 18-2: User LEDs on the FPGA Board User LEDs Pin Assignment: Pin Name FPGA Pin LED1 LED2 LED3 LED4 Part 19: Buttons The AX530 FPGA development board has five independent buttons, 49 / 53 www.alinx.com...
  • Page 50 Cyclone IV FPGA Development Board AX530 User Manual including four user buttons (KEY1~KEY4) and one reset button RESET. The buttons are active low, and the schematic diagram of the four user buttons is shown in Figure 19-1 Figure 19-1: Four User Button Schematic The reset button is connected to the normal IO of FPGA for reset FPGA program.
  • Page 51 Cyclone IV FPGA Development Board AX530 User Manual Buttons Pin Assignment Button Name FPGA Pin Key name KEY1 KEY 1 KEY2 KEY 2 KEY3 KEY 3 KEY4 KEY 4 RESET RESET Part 20: 7-segment displays The digital tube is a very common display device. It is generally divided into a seven-segment digital tube and an eight-segment digital tube.
  • Page 52 Cyclone IV FPGA Development Board AX530 User Manual The six-in-one digital tube is a dynamic display. Due to the persistence of human vision and the afterglow effect of the LED, although the digital tubes are not lit at the same time, as long as the scanning speed is fast enough, the impression is a group, stable display data, no flickering.
  • Page 53 Cyclone IV FPGA Development Board AX530 User Manual Figure 20-3: 7-segment displays on the FPGA board 7-segment displays Pin Assignments: Pin Name FPGA Pin Description SMG_Data[7] Corresponding segment DP SMG_Data[6] Corresponding segment G SMG_Data[5] Corresponding segment F SMG_Data[4] Corresponding segment E...

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