Intel SR1530AHNA Technical Product Specification page 61

Server chassic and server system
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Intel® Server Chassis SR1530
Intel® Server System SR1530AH
Diagnostic LED Decoder
Checkpoint
G=Green, R=Red, A=Amber
MSB
Host Processor
0x10h
OFF
OFF
0x11h
OFF
OFF
0x12h
OFF
OFF
0x13h
OFF
OFF
Chipset
0x21h
OFF
OFF
Memory
0x22h
OFF
OFF
0x23h
OFF
OFF
0x24h
OFF
G
0x25h
OFF
G
0x26h
OFF
G
0x27h
OFF
G
0x28h
G
OFF
PCI Bus
0x50h
OFF
R
0x51h
OFF
R
0x52h
OFF
R
0x53h
OFF
R
0x54h
OFF
A
0x55h
OFF
A
0x56h
OFF
A
0x57h
OFF
A
USB
0x58h
G
R
0x59h
G
R
ATA / ATAPI / SATA
0x5Ah
G
R
0x5Bh
G
R
SMBUS
0x5Ch
G
A
0x5Dh
G
A
Local Console
0x70h
OFF
R
0x71h
OFF
R
0x72h
OFF
R
Remote Console
Revision 1.0
Appendix B: POST Code Diagnostic LED Decoder
Table 32. Diagnostic LED POST Code Decoder
LSB
OFF
R
Power-on initialization of the host processor (bootstrap processor)
OFF
A
Host processor cache initialization (including AP)
G
R
Starting application processor initialization
G
A
SMM initialization
R
G
Initializing a chipset component
A
OFF
Reading configuration data from memory (SPD on DIMM)
A
G
Detecting presence of memory
R
OFF
Programming timing parameters in the memory controller
R
G
Configuring memory parameters in the memory controller
A
OFF
Optimizing memory controller settings
A
G
Initializing memory, such as ECC init
R
OFF
Testing memory
OFF
R
Enumerating PCI busses
OFF
A
Allocating resources to PCI busses
G
R
Hot Plug PCI controller initialization
G
A
Reserved for PCI bus
OFF
R
Reserved for PCI bus
OFF
A
Reserved for PCI bus
G
R
Reserved for PCI bus
G
A
Reserved for PCI bus
OFF
R
Resetting USB bus
OFF
A
Reserved for USB devices
G
R
Resetting PATA / SATA bus and all devices
G
A
Reserved for ATA
OFF
R
Resetting SMBUS
OFF
A
Reserved for SMBUS
R
R
Resetting the video controller (VGA)
R
A
Disabling the video controller (VGA)
A
R
Enabling the video controller (VGA)
Intel order number D77400-002
Description
III

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