Sunsea AIoT SIMCom SIM7075G User Manual page 34

Table 16: PCM timing parameters
Parameter Description
T(sync) PCM_SYNC cycle time
T(synch) PCM_SYNC high level time
T(syncl) PCM_SYNC low level time
T(clk) PCM_CLK cycle time
T(clkh) PCM_CLK high level time
T(clkl) PCM_CLK low level time
PCM_SYNC setup time high before falling edge of
T(susync)
PCM_CLK
PCM_SYNC hold time after falling edge of
T(hsync)
PCM_CLK
PCM_IN setup time before falling edge of
T(sudin)
PCM_CLK
T(hdin) PCM_IN hold time after falling edge of PCM_CLK
T(pdout) Delay from PCM_CLK rising to PCM_OUT valid
Delay from PCM_CLK falling to PCM_OUT
T(zdout)
HIGH-Z
3.7.2 PCM Application Guide
www.simcom.com
Figure 20: External codec to module timing
Figure 21: Module to external codec timing
SIM7075G User Manual V1.00
Min. Typ. Max.
– 125 –
– 488 –
124.5
– –
– 488 –
– 244 –
244
– –
– 122 –
– 366 –
60
– –
60 – –
– – 60
– – 60
Unit
μs
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
34 / 74