Analog Devices EVAL-AD9959 User Manual page 9

User Guide
EVALUATION BOARD SOFTWARE
FEATURE CONTROL WINDOWS
Chip Level Control
The Chip Level Control window provides control of the features
that affect all channels of the AD9959; this window is not channel-
specific. The following describes the sections of the chip level
control window as they are numerically indexed in
1. LOAD and READ
The LOAD and READ buttons are used to send data and retrieve
register settings. All LOAD and READ buttons found in the evalua-
tion software have the same functionality.
When new data is detected, LOAD flashes orange, indicating that
you need to click LOAD to send the updates to the serial I/O buffer
where they are stored until an I/O update is issued. The I/O update
sends the contents of the serial I/O buffer to active registers.
I/O updates can be sent manually (Manual I/O Update) or auto-
matically (Auto I/O Update). By default, the AD9959 evaluation
software is set to Auto I/O Update, so that when LOAD is clicked,
an I/O update signal is automatically sent to the device. If synchro-
nization across channels is desired, use the Manual I/O Update
button. To do this, uncheck the Auto I/O Update box and press the
Manual I/O Update button when you wish to send an I/O update
(see Figure 18).
Figure 18.
Click READ to perform a readback of the current state of the
settings and update the GUI with those settings.
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Figure 17. Chip Level Control Window
2. Clock
The Clock section allows the user to configure the reference clock
path in the AD9959.
Figure 17.
Ref Clock inputs the operating frequency of the external reference
clock or crystal. The maximum reference clock frequency of the
AD9959 is 500 MHz, which is the default setting of this box. A red
outline indicates that the value entered is out of range. (See
19).
Multiplier selects the PLL multiplication factor (4× to 20×) by which
to scale the input frequency. The default setting of this box is Disa-
bled, indicating that the Ref Clock Multiplier circuitry is bypassed
and the Ref Clock/Crystal input is piped directly to the DDS core.
CP Current selects the charge pump current output of the PLL
in the Ref Clock Multiplier circuitry. Selecting a higher current
output will result in the loop locking faster, but there is a trade-off.
Increasing this current output will also increase phase noise. The
default setting of this box is 75 μA.
EVAL-AD9959
Figure 19.
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Figure