Analog Devices EVAL-AD9959 User Manual page 3

User Guide
EVALUATION BOARD HARDWARE
PACKAGE CONTENTS
The AD9959/PCB kit contains the following:
AD9959 evaluation board
►
AD9959/PCB installation software
►
REQUIREMENTS
In order to successfully use the evaluation board and run the
software, the requirements listed in
Table 1. AD9959/PCB Requirements
Item Requirement
Operating System Windows
®
Processor Pentium
Memory 128 MB or better
Ports One USB port
Clocking Signal generator capable of generating sinusoidal
waves of at least 3 dBm power, up to at least 10
MHz
Power Supplies Capability to generate at least 2 independent dc
voltages (1.8 V/3.3 V)
Measurement Appropriate measurement device, such as a spectrum
analyzer or a high bandwidth oscilloscope
Cables USB 1.1/2.0 cable, and SMA-to-X cables (X = SMA
or BNC, depending on the connector of the device
interfacing with the board)
SETTING UP THE EVALUATION BOARD
Powering the Part
The AD9959 evaluation board has seven power supply connectors:
TB1, J10, J16, J17, J18, J19, and J20. TB1 powers the DDS, the
PC interface logic, and the USB circuitry. J10 powers the input
clock circuitry. J18 provides the reference voltage needed for band
gap functionality. J16, J17, J19, and J20 power the analog circuitry
of individual DACs. It is important to keep in mind that the AD9959
evaluation board has been preconfigured so that these four AVDD
connections (J16, J17, J19, and J20) are tied together. Supplying
power to any one of the AVDD connections allows for the proper
functionality of the analog circuitry of all four DACs.
the necessary connections and the appropriate biasing voltage.
Table 2. Connections and Biasing Voltage
Connector Pin No.
TB1 1
TB1 2
TB1 3
TB1 4
J10
analog.com
Table 1 must be met.
®
98/Me/2000/XP
I or better
Table 2 shows
Label Voltage (V)
VCC_USB 3.3
DVDD_I/O 3.3
GND 0
DVDD 1.8
CLK_VDD 1.8
Table 2. Connections and Biasing Voltage (Continued)
Connector Pin No.
J16
J17
J18
J19
J20
Note that the AD9959/PCB is preconfigured so that the CLK_VDD,
BG_VDD, and all other AVDD connections are tied together. There-
fore, only one connection (J10, J16, J17, J18, J19, or J20) needs
power for proper functionality of all four channels. These AVDD
connections can be separated for better channel isolation. This is
accomplished by removing the 0 Ω resistors (R21, R32–R51, R54–
R64) that tie the planes together found on the back of the evalua-
tion board. When doing this, be sure that CLK_VDD, BG_VDD, and
the AVDD connection for all desired channel(s) are powered.
Clocking the Part
The AD9959 architecture provides the user with two options when
providing an input signal to the part.
can clock the frequency synthesizer/DDS directly by connecting
an external clocking signal to the REF CLK connector, J9, or by
providing an external crystal. Place jumper W11 on REF CLK to
use the external clocking option. To use an external crystal as the
clocking source, place jumper W11 on CRYSTAL.
Refer to the AD9959 data sheet for details on the maximum input
speeds and input sensitivities of these two inputs.
Communicating With the Part
Two interface standards are available on the evaluation board:
1. USB 1.1/2.0 interface.
2. Header row (U2, U13), which places the part under the control
of an external controller (such as a µP, FPGA, or DSP).
Analog Devices provides a GUI for the PC; it does not provide
control software for external controllers.
Use the jumper settings listed in
of communication.
Table 3. Jumper Settings for Communication Modes
Mode Settings
PC control, USB port Set W7 to PC. Place a jumper on W1, W2, W3,
W9, and W10.
External control Set W7 to manual. Place a jumper on W9, and
remove W1, W2, W3, and W10 (or leave it stored
as a shunt).
EVAL-AD9959
Label Voltage (V)
AVDD 1.8
AVDD 1.8
BG_VDD 1.8
AVDD 1.8
AVDD 1.8
Figure 1 shows that the user
Table 3 to enable different modes
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