Table Of Contents - Tektronix RTD 710A Service Manual

Section 1. THEORY OF OPERATION (Cont.)
Comparator 2.6... . ee ee 1-42
TriggerLevei ........... 1-42
TRIGGER SLOPE CONTROL
(21 a 1-45
Trigger Generator and Slope
Selector 2... ee ee 1-45
TRIGGER MPU INTERFACE
(Dia. 18) 2. ee ee 1-48
Probe Calibration Signal Generator 1-48
TRIGGER MPU INTERFACE 2
(Dia. 17,18, 19) ....-...04. 1-48
Trigger Source Select Control. . 1-48
Trigger Coupling Control... . . 1-48
Trigger Slope Select Control . . . 1-48
Trigger Readback ......... 1-48
TV Trigger Setup 2. 2. 2 ew, 1-48
TV Trigger Readback ....... 1-48
Address Decoders 22... 1. 1-48
Silent MPU Bus Buffer 2.2... 1-50
ACQUIRED DATA STORAGE ... . 1-50
CHANNEL 1 INPUT AND DIRECT A/D
OUTPUT (Dia. 20) .......0... 1-53
Channel 1 First Latch Timing
Generator... 2.2.2 ee ee 1-53
Channel 1 First Latch and Second
Latch 2.0... cee ee ee 1-54
Channel 1 Odd and Even Data
Registers ..........00- 1-54
Channel 1 Direct A/D Output Butfer 1-54
Trigger Signai Timing Adjuster . . 1-54
CHANNEL 2 INPUT AND DIRECT A/D
OUT (Dia. 21)... ee 1-55
Channei 2 First Latch/Clock Buffer 1-55
Channel 2 Odd Data Register/Even
Data Register ........20.. 1-56
Channel 2 Direct A/D Out Buffer . 1-56
CHANNEL 1 COMPARATOR AND
SYNCH DATA LATCH (Dia. 22) . . . 1-56
CHANNEL. 2 COMPARATOR AND SYNC
DATA LATCH (Dia. 23). ....... 1-57
ACQUISITION TIMING GENERATOR
(Dia, 24) 2. ee ee ee 1-57
Two-Phase Clock Generator and
Two-Phase Clock Buffer 2.1... 1-58
Shift Clock Generator... 1... 1-58
Memory Latch Clock Generator . . 1-59
MEMORY ...........0005 1-60
ECL-TTL TRANSLATOR AND HIGH-
SPEED SHIFT RESISTER (Dia. 25) . 1-60
MEMORY STORAGE LATCH
(Dia. 26)... ee eee 1-60
WAVEFORM MEMORY
(Dia. 26827). ........0... 1-60
MEMORY MPU INTERFACE
(Dia. 28) 2. ee ee 1-61
Memory Data Buffer... 2... 1-61
Data Bus Buffer... 1... 1-61
TIME BASE... 2.2... ee 1-61
Section 1 THEORY OF OPERATION (Cont.)
ARM AND TRIGGER (Dia. 29) ... . 1-61
Addrass Decoder .........- 1-61
Arm-Start Flip Fop 6. 0 ee 1-61
1OkHz Oscillator 2. 2... 1-64
Internal Arm Delay Divider... . . 1-64
Arm Moda Selector... 1.4... 1-64
Trigger Control 6... 2. ee. 1-64
One-Shot Pulse Generator... . 1-64
Trigger Signal Generator... . . 1-64
BREAKPOINT LOCATOR (Dia. 30). 1-64
MPU Interface Buffer 2. ..... 4-65
Breakpoint Location RAM .... . 1-66
Breakpoint Location RAM Address
Counter 2... ee ee ee 1-66
Address Counter Clock Generator 1-66
Breakpaint Location Counter . . . 1-66
Comparator 2... 2... wee 1-66
Mode ControlLatch 2. ...... 1-66
Arm Delay DriverLatch ...... 4-66
INTERVAL DATA RAM (Dia. 31) . . . 1-87
Sampling Interval RAM, TTL-ECL
Translator, and Gates ....... 1-67
Ratelatch 2.2.2... 2.00000. 1-70
A/D Overtiow Data Buffer... . . 1-74
Control Signal Levai Transiator . . 1-71
PROGRAMMABLE COUNTER
(Dia. 32) 0. ee 1-74
Pre-Sealer Divider... 0.0.00. 1-71
Decade Divider .......... 4-71
SAMPLE CLOCK GENERATOR
(Dia. 33a&33b) 2.2... Le 1-73
Clock Buffer 2... . 0.0.0. 1-73
Phase Calibration Clock Generator 1-74
Envalope Clock Generator... . 1-74
1/2 Divider and Buffar . 2... 2... 1-74
Gata 2... ee 1-74
High Spaed Made Sample Clack
Generator 2. ee 1-74
Normal Mode Sample Ciock
Generator 2. 0. 1-74
Breakpoint Location Counter Clock
Generator 2... ee 1-74
Rate Latch Clock Generator .. . . 1-75
Fast Clock Switcher ........ 1-75
Synchronize Circuit ... 2.0... 1-75
SAMPLE CLOCK OUTPUT AND
200 MHZ OSC (Dia. 34). 2. 1-78
Normal Mode Sample Clock Delay 1-78
Gate With Complementary Output 1-78
VariableDelay ........... 1-78
CH1 Clock Delay Adjust... ... 1-79
Selector 2. 2 ee 1-78
Envelope Clock Gate... 2... 1-79
200 MHZOSC «ww. ee 1-79
ADDRESS GENERATOR ...... 1-79
MEMORY ADDRESS (Dia. 35} . . . . 1-81
Address Shift 2... ..0.042, 1-81
Address Decoda ... 2... 0. 1-82
RTD 710A Service Manual