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ADLINK Technology PCIe-7442 User Manual

64ch isolated di/64ch isolated do pcie card
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64CH Isolated DI/64CH Isolated DO PCIe Card
Manual Rev.:
Revision Date:
Part No:
Advance Technologies; Automate the World.
This datasheet has been downloaded from
PCIe-7442
User's Manual
2.00
Dec. 30, 2016
50-11264-1000
http://www.digchip.com
at this
page

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Summary of Contents for ADLINK Technology PCIe-7442

  • Page 1 PCIe-7442 64CH Isolated DI/64CH Isolated DO PCIe Card User’s Manual 2.00 Manual Rev.: Dec. 30, 2016 Revision Date: 50-11264-1000 Part No: Advance Technologies; Automate the World. This datasheet has been downloaded from http://www.digchip.com at this page...
  • Page 2 Revision History Revision Release Date Description of Change(s) 2.00 Dec. 30, 2016 Initial release...
  • Page 3 PCIe-7442 Preface Copyright ©2016 ADLINK Technology, Inc. This document contains proprietary information protected by copy- right. All rights are reserved. No part of this manual may be repro- duced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 4 Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. Additional information, aids, and tips that help users perform tasks. NOTE: NOTE: Information to prevent minor physical injury, component dam- age, data loss, and/or program corruption when trying to com- plete a task.
  • Page 5 PCIe-7442 Table of Contents Revision History..............ii Preface ..................iii List of Figures ............... vii List of Tables................ix 1 Introduction ................ 1 Features................1 Applications ................. 2 Specifications............... 2 Software Support ..............3 PCIS-DASK ..............3 PCB Layout................4 Connectors ................
  • Page 6 COS Interrupt Control Registers ........21 COS Setup/Latch Registers..........23 TTL I/O Setup, Status, DO, and DI Registers ....24 Isolated Digital Output and Read Back Registers....25 Power-up DO Setup/Read Register........26 Watchdog Timer Load, Safety DO Setup/Read Back Registers................
  • Page 7 PCIe-7442 List of Figures Figure 1-1: PCIe-7442 Board Layout ..........4 Figure 1-2: CN1/CN2 Connector............5 Figure 1-3: CN1A Connector ID ............6 Figure 1-4: CN1B Connector ID ............7 Figure 1-5: CN2A Connector ID ............9 Figure 1-6: CN2B Connector ID ............10 Figure 1-7: I/O Connector ..............
  • Page 8 This page intentionally left blank. viii List of Figures...
  • Page 9 PCIe-7442 List of Tables Table 1-1: PCIe-7442 Board Layout Legend ........4 Table 1-2: CN1 Connector Pin Assignment ........8 Table 1-3: CN2 Connector Pin Assignment ........11 Table 1-4: JP3 I/O Connector Pin Assignment ....... 12 Table 1-5: JP4 I/O Connector Pin Assignment ....... 12 Table 2-1: Board ID Setting Conditions ..........
  • Page 10 This page intentionally left blank. List of Tables...
  • Page 11 PCIe-7442 Introduction ADLINK'S PCIe-7442 is a basic digital I/O card for PCIe bus com- puters in industrial applications. All digital input channels are identical non-polar and opto-isolated, suitable for collecting digital input in noisy environments. COS (Change of state) interrupt is supported, whereby when any digital input changes state, an interrupt is generated to allow manage- ment of the event.
  • Page 12 1.2 Applications Industrial ON/OFF control  External high power relay driving, signal switching  Laboratory automation  Industrial automation  Switch contact status detection and limit switch monitoring  & control systems 1.3 Specifications Digital Input Input channels Photocoupler PC3H4 10 mA rated Input current 50 mA max.
  • Page 13 PCIe-7442 Operating temperature 0 to 60°C Storage temperature -20 to 80 °C Humidity 5 to 95% non-condensing 1x PCI Express +12V@170mA (typical) 300mA (Max.) +3.3V@ 1mA (typical) 1.5mA (Max.) Power consumption (when all relays are activated simultaneously) 1.4 Software Support ADLINK provides comprehensive software solutions for all system building requirements.
  • Page 14 Figure 1-1: PCIe-7442 Board Layout 16CH (TTL15 to 31) TTL I/O connector 16CH (TTL 0 to 15) TTL I/O connector Board ID DIP switch 64CH isolated digital output connector 64CH isolated digital input connector Table 1-1: PCIe-7442 Board Layout Legend Introduction...
  • Page 15 PCIe-7442 1.6 Connectors The PCIe-7442 is equipped with a 68-pin Dual port VHDCI con- nector, via CN1A, CN1B, CN2A, and CN2B. CN2B CN2A CN1B CN1A Figure 1-2: CN1/CN2 Connector IDI_0 IDI_8 IDI_1 IDI_9 IDI_2 IDI_10 IDI_3 IDI_11 Introduction...
  • Page 16 IDI_4 IDI_12 IDI_5 IDI_13 IDI_6 IDI_14 IDI_7 IDI_15 COM1 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 COM2 IDI_16 IDI_24 IDI_17 IDI_25 IDI_18 IDI_26 IDI_19 IDI_27 IDI_20 IDI_28 IDI_21 IDI_29 IDI_22 IDI_30 IDI_23 IDI_31 COM3 COM4 COM3...
  • Page 17 PCIe-7442 COM8 COM7 COM8 COM7 COM8 COM7 COM8 COM7 COM8 COM7 COM8 COM7 COM8 COM7 IDI_63 IDI_55 IDI_62 IDI_54 IDI_61 IDI_53 IDI_60 IDI_52 IDI_59 IDI_51 IDI_58 IDI_50 IDI_57 IDI_49 IDI_56 IDI_48 COM6 COM5 COM6 COM5 COM6 COM5 COM6 COM5 COM6...
  • Page 18 Definition IDI_n Isolated digital input channel n COM1 Common VDD junction for input channels 0-7 COM2 Common VDD junction for input channels 8-15 COM3 Common VDD junction for input channels 16-23 COM4 Common VDD junction for input channels 24-31 COM5 Common VDD junction for input channels 32-39 COM6 Common VDD junction for input channels 40-47 COM7 Common VDD junction for input channels 48-55 COM8 Common VDD junction for input channels 56-63...
  • Page 19 PCIe-7442 IDO_17 IDO_25 IDO_18 IDO_26 IDO_19 IDO_27 IDO_20 IDO_28 IDO_21 IDO_29 IDO_22 IDO_30 IDO_23 IDO_31 VDD3 VDD4 IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND Figure 1-5: CN2A Connector ID IGND IGND IGND IGND...
  • Page 20 IDO_57 IDO_49 IDO_56 IDO_48 IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND VDD6 VDD5 IDO_47 IDO_39 IDO_46 IDO_38 IDO_45 IDO_37 IDO_44 IDO_36 IDO_43 IDO_35 IDO_42 IDO_34 IDO_41 IDO_33 IDO_40 IDO_32 Figure 1-6: CN2B Connector ID Definition IDO_n Isolated digital output channel n...
  • Page 21 PCIe-7442 Definition Onboard unregulated 5V power supply output No connection Table 1-3: CN2 Connector Pin Assignment DI/O Connections Figure 1-7: I/O Connector TTL I/O channel n TTLIO_n System ground for PCIe-7442 card SGND Function Function TTLIO_0 TTLIO_8 TTLIO_1 TTLIO_9 Introduction...
  • Page 22 The isolated digital input, with open collector transistor structure, supports voltage range of 0 to 28V with input resistance 4.7K. Connection between external signals and the PCIe-7442 is as shown. Since the input common junction can be common ground Introduction...
  • Page 23 PCIe-7442 with the existing environment, digital input can be current source or current sink. Current Flow DICOM (GND) Current Flow DICOM (+VDD) Figure 1-8: Isolated Input Connection 1.8.2 Isolated Digital Output Channels In the common ground connection of isolated digital output, as shown, when isolated digital output goes ON, sink current passes through the transistors until output is OFF.
  • Page 24 COS Detection Architecture The COS interrupt system generates an interrupt request signal which is serviced request with ISR. The PCIe-7442 has bank 0 from DI0 to DI31 and bank 1 from DI32 to 63, cascaded together toward the same IRQ line via CPLD. Notification can be config-...
  • Page 25 COS function for each is disabled as default. 1.10 Programmable Power Up DO Status The PCIe-7442 provides programmable configuration of all 64CH DO initial status when powering up. As well, the system can be configured to hold DO status and avoid power-up initial configura- tion after a hot system reset.
  • Page 26 This page intentionally left blank. Introduction...
  • Page 27 Retain the shipping carton and packing mate- rials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Ensure that the following items are included in the package. PCIe-7442 high-speed DI/O card  Quick Start Guide ...
  • Page 28 6. Replace the system/chassis cover. 7. Connect the power plug to a power source, then turn on the system. Configuration All PCI/PCIE Express cards on your system are configured individ- ually. Because configuration is controlled by the system and the software, no jumper setting is required for base address, DMA, and interrupt IRQ.
  • Page 29 PCIe-7442 Switch Board ID Table 2-1: Board ID Setting Conditions Getting Started...
  • Page 30 This page intentionally left blank. Getting Started...
  • Page 31 PCIe-7442 I/O Registers 3.1 About PCIe Controller Registers The PCIe-7442 function library provides simple and easy-to-use functions to mange interrupt procedures. The functions eliminate the need to manipulate the interrupt register in the PCIe controller. It is recommended to use these functions to avoid the effort in developing all-new interrupt functions.
  • Page 32 The COS interrupt is enabled by two registers. Because the 64 digital inputs are divided into two 32-bit onboard buses, every 32 inputs are connected to a CPLD. When COS interrupt EA0 (BASE+0x06h) is enabled, the first CPLD (CPLD0) generates an interrupt signal when the first 32 inputs IDI [31..0] experience state change.
  • Page 33 PCIe-7442 3.4 COS Setup/Latch Registers Change of State (COS) interrupt is provided on any digital input channel, allowing status of digital input channels to be monitored by setting registers as follows. Enabling COS Setup registers generates an interrupt when the corresponding channel changes its state.
  • Page 34 Address: BASE+0x06h Reset Value: 0x0000h Read/Write: W CLR0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 3.5 TTL I/O Setup, Status, DO, and DI Registers An extra 32CH TTL I/O function is provided for optional applica- tions.
  • Page 35 PCIe-7442 Address Value Mapping (MSB----LSB) BASE+0x0Eh TTL_IO_DO[15…0] BASE+0x4Eh TTL_IO_DO[31...16] When the I/O direction setting is input, data can be read through the TTL I/O input channel, with bit value 0 setting input low and 1 high (initial value). Address Value Mapping (MSB----LSB) BASE+0x0Eh TTL_IO_DI[15…0]...
  • Page 36 BASE+0x88h IDO[63...48] 3.7 Power-up DO Setup/Read Register When the system powers up, the PCIe-7442 can initiate transmis- sion of default initial value to 64CH digital outputs. The power-up default DO values can be configured and stored in flash memory, such that DO assumes a specified status at power up. Default 64CH power-up default DO values can be programmed via the Power-up DO Setup Register in turn.
  • Page 37 64CH safety DO values are stored in the flash memory. When WDT interrupt asserts and the SafetyOut_Enable bit is enabled, the PCIe-7442 enters the safety DO procedure which sends out the default safety value to 64CH digital outputs. 64CH safety default DO values can be programmed by accessing the previous WDTSafety DO Setup register in turn.
  • Page 38 3.9 WDT INT Control, Hot-Reset, and Hold Control Register The PCIe-7442 supports COS INT and watch dog timer (WDT) interrupt modes. When enabled, the WDT counts down as a mode of intrrupt, and is asserted when the counter reaches zero. WDT...
  • Page 39 PCIe-7442 and prevent possible system damage. According to user settings, when the system experiences unexpected or normal hot system reset without proper power down, the board can retain the original pre-rest DO values, or enter the power-up initial procedure to issue the previously configured default initial DO values.
  • Page 40 Address: BASE+0x8Ah Reset Value: 0x0000h Read/Write: R Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Function HRHES: Hot Reset Hold Enabled Disabled Enable Status WDTES: WDT Interrupt Enabled Disabled Enable Status WDT interrupt WDT interrupt WIS: WDT Interrupt Status does not assert...
  • Page 41 PCIe-7442 Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures...
  • Page 42 Never attempt to repair the device, which should only be  serviced by qualified technical personnel using suitable tools A Lithium-type battery may be provided for uninterrupted  backup or emergency power. Risk of explosion if battery is replaced with one of an incorrect type;...
  • Page 43 PCIe-7442 BURN HAZARD Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching. RISQUE DE BRÛLURES Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher.
  • Page 44 This page intentionally left blank. Important Safety Instructions...
  • Page 45 San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: (201203) 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com...
  • Page 46 84 Genting Lane #07-02A, Cityneon Design Centre Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office) Address: #50-56, First Floor, Spearhead Towers Margosa Main Road (between 16th/17th Cross) Malleswaram, Bangalore - 560 055, India Tel: +91-80-65605817, +91-80-42246107 Fax:...