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3x 40 pins expansion connectors on the reconfigurable unit I/Os 1x 16 pins expansion connector for processor PIO 1 Debug Support Unit connector (DSU) for ATF697FF LEON2 SPARC processor debugging On board Space Programmer unit Evaluation Board ATF697FF V2.1 [USER GUIDE]...
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This document describes the evaluation board V2.1 dedicated to ATMEL ATF697FF configurable processor. The ATF697FF is a multi-chip module made of an ATMEL AT697F die together with an ATMEL ATF280F die. This allows extension of the 32-bit SPARC® V8 processor functionalities by adding a user dedicated area made of a 280 Kgate FPGA.
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Board display ..................34 2.13.4 Reconfigurable units dedicated press buttons ........35 2.14 UART interface....................35 2.14.1 Serial link 1 ..................35 2.14.2 Serial link 2 ..................36 2.15 CAN interface ....................37 Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Clocks test points ................39 2.17.3 System test points ................40 2.18 Expansion connector ..................41 3. Appendix A – Space Programmer Update ........44 4. Revision History ................45 Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Overview Figure 1-1 ATF697FF Evaluation board v2.1 Deliverables The ATF697FF evaluation board is delivered with: 1x LCD screen 240x320 pixel, 16bits color deep 6x Bumpers Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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1x Reconfigurable Unit reset LED 1x Processor reset LED 1x Reconfigurable Unit OTS press button 1x Reconfigurable Unit CHECKn press button 3x LEDs for ATF697FF board activity (run, boot, error). Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Hardware description Block diagram Following figure gives an overview of specific modules connected with only one device of the ATF697FF: processor part or reconfigurable unit part. Figure 2-1 ATF697FF Evaluation Kit Processor and r econfigurable u nit diagram Processor user...
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Some evaluation kit features are connected to both processor and reconfigurable unit parts. Following diagram shows how these modules are arranged together. Figure 2-2 ATF697FF Evaluation Kit common parts diagram Reset management Serial EEPROM ATF697FF management monitoring I²C status ATF697FF...
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SW20.4 Configure the processor as the master and reconfigurable unit as the slave SW20.5 Disable monitoring SW20.6 LCD display use serial connection SW20.7 N.C. SW20.8 N.C. SW20.9 N.C. SW20.10 N.C. Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Power supplies sources With the default configuration, the ATF697FF Evaluation Kit shall be powered from the 2.1mm Jack connector with an 8V to 12V power supply source. A power supply source capable to deliver up to 10W shall be used (10W figure can be achieved when daughter boards are connected to the expansion connectors).
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2.4.2 Power supplies current measurement The ATF697FF Evaluation Board offers the possibility to have an overview of the power consumption of components. Current measurement test points are arranged according to the following drawing: Figure 2-5 Current probe footprint 2.54mm 2.54mm 2.54mm...
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Current and voltage test pads are accessible close to power supply regulations as shown in the following figures: Figure 2-8 Power supply indicators Processor pll (1,8V) PROC 1V8 FPGA 1V8 FPGA 3V3 Device 1V8 Board 1V8 Device 3V3 Board 3V3 Device 1V25 Board 5V Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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EEPROM SEREN A1 (AT17) PIO 6 LCD CS EEPROM SEREN A2 (AT17) PIO 7 ADC CS EEPROM SEREN B (AT69) PIO 8 HMI PB ENTER I2C DATA PIO 9 Reconfigurable unit reset control Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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SW20.5 should be “ON” to connect ERRORn (from processor) to IO763 (reconfigurable unit pin 115) PIO3 should be “ON” to allow PIO11 to be connected to INIT (reconfigurable unit pin 294) Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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2.6.2.1 PROM Overview The ATF697FF processor is able to work with two bus widths: 8 bits or 32 bits. In both cases, the processor can use the EDAC mode. If EDAC is enabled on the PROM 32, the processor needs 8 more bits so total bus length is 40 bits in this case.
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Enabled IMPORTANT: PROM8 is not recognized by GRMON. The ATF697FF processor PROM bus width is configured at reset time according to PIO[1:0] value. Under reset the processor samples PIO[1:0] and reports its value to the memory configuration register MCFG1. Figure 2-12 PROM implantation...
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2.6.2.4 PROM Expansion The ATF697FF processor can control up to 512Mbytes of PROM. The evaluation board can handle up to 16M bytes of PROM code. For applications that need more PROM capacity, it is possible to extend the total PROM capacity by connecting a daughter board to the expansion connectors.
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Bottom side 2.6.3.3 RAM Expansion The ATF697FF processor can control up to 1Gb of SRAM and/or SDRAM. For applications that need more RAM capacity, it is possible to extend the total RAM capacity by connecting a daughter board to the expansion connectors.
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2.7.2 Memory organization overview Reconfigurable unit in master mode: The reconfigurable unit embedded in the ATF697FF requires up to 4Mbits memory for its configuration. The 4 Mbits of serial EEPROM memory are built around two space qualified devices: Four cascaded AT17LV010 devices (1Mbit / device) ...
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PIO 12 B EEPROM selection SW8 PIO 2 B PIO 7 B DEMUX PIO 6 B PIO 5 B ATF697FF Processor Legend: ATF697FF I²C User interface switch Chip select Connector EEPROM ready Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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AT17 (3) connected to CS2_AT17 and with the A2 line driven to ‘GND’ shall be addressed, to finish the AT17 (4) connected to CS2_AT17 and with the A2 line driven to ‘VDD’ shall be addressed. Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Five clocks are created by an on board clock generator (CDCE925 circuit family). The circuit can be configured through different ways: By the processor. By the space programmer (the method is explained in appendix C). Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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SW19.3 OFF: SKEW0 disabled ON: SKEW0 enable SKEW 1 SW19.4 OFF: SKEW1 disabled ON: SKEW1 enable SW19.6 OFF: processor use on-board 25MHz clock ON: processor use Clock EXT IN 1 Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Evaluation Kit Reset The following figure shows a general view of reset mechanism of the evaluation kit: Figure 2-19 Reset overview Note: reset signals are all active at low level. Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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By using SW37.5, it’s possible to connect processor Watchdog pin WDOG (pin 148) to the processor reset module. Table 2-12 Watchdog configuration Name Switch number Function Processor pin OFF: disconnect WDOG pin to reset module Watchdog SW19.5 ON: connect WDOG pin to reset module Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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(by detecting INIT signal low while CCLK is running) Otherwise, the led is OFF. The following flowchart describes the behavior of the internal signal which control the leds behavior. Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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A DSUBRE Press button to allow the user to put the processor in debug mode. The ATF697FF processor Debug Support Unit is based on a RS232 serial link connected to a host platform. The ATF697FF evaluation board includes all the required hardware to manage the RS232 communication and the debug facilities.
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Multi channels ADC 2.12 The ATF697FF evaluation board embeds 8 channels 12bits Analogue to Digital Converter from Analogue Devices: the AD7888. The device is connected to the processor and the reconfigurable unit through SPI connection as shows le following table:...
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ADC channel Sampled signal 3.3V Voltage supplying ATF697FF Consumed current by 3.3V by the ATF697FF 1.8V Voltage supplying ATF697FF Consumed current by 1.8V by the ATF697FF Voltage from SMB connector N.C. The current measurement is done through a 0.01 ohm resistor. Because the measured differential signal is very small, an amplifier used as non inverted differential boost the signal to allow good conversion of the ADC.
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IO537 HMI_LCD_D4 Data bus D4 IO553 HMI_LCD_D5 Data bus D5 IO563 HMI_LCD_D6 Data bus D6 IO567 HMI_LCD_D7 Data bus D7 IO573 (1): To use this function, PIO3 should be low Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Figure 2-27 R econfigurable u nit button implementation UART interface 2.14 The ATF697FF evaluation board includes all the required hardware to manage a RS232 communication. Hardware flow control (CTS & RTS) are not implemented on this Evaluation Kit. 2.14.1 Serial link 1 Serial link 1 is available on the board through the UART 1 connector.
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Serial link 2 is available through the expansion connector only and is only 3.3V tolerant. If serial link 2 is connected to a RS232 interface on an expansion board, a line driver (like MAX3232) has to be implemented to adapt voltage. Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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CAN interface 2.15 The evaluation kit embeds two serial CAN links in one standard DB9 connector. An ATA6660-TAPY transceiver converts and adapts ATF697FF signals to standard CAN serial interface. Table 2-21 CAN ATF697FF mapping Serial link name Processor connection Reconfigurable unit...
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Function DIN+ SIN+ SOUT- DOUT- DIN- SOUT+ DOUT+ The SpaceWire interfaces are connected to the ATF697FF reconfigurable unit LVDS interface as defined in the following tables: Table 2-24 SPW1 assignment ATF697FF reconfigurable unit signals Signal name ATF697FF pin FPGA_ILVDSA1 DIN1+...
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Current measurement test points are arranged according to the following drawing: Figure 2-28 Press button implementation 2.54mm 2.54mm 2.54mm R shunt 0.01R B, C 2.17.2 Clocks test points Figure 2-29 Clock test points Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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2.17.3 System test points Figure 2-30 System test points ERRORn / CLK / BEXC FCKA / CCLK / GCK7 / D0 GCK3 GCK5 INIT FPGA test pad: Processor test pad: Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Appendix A – Space Programmer Update See troubleshooting document (41044B) if a space programmer firmware update is needed. Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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Table 4-1 Board history Version Comments 41002A Release with Board V1.2 41002B Release with Board V2.1.1 41002C Add section to update Space Programmer firmware 41002D Add section for led Run, boot & fail Evaluation Board ATF697FF V2.1 [USER GUIDE] 41002D – AERO 01/16...
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